[Intel-gfx] [PATCH v2 5/6] drm/i915/fbc: Split plane pixel format checks per-platform
Ville Syrjala
ville.syrjala at linux.intel.com
Tue Oct 3 19:42:55 UTC 2023
From: Ville Syrjälä <ville.syrjala at linux.intel.com>
Carve up pixel_format_is_valid() into per-platform variants to
make it easier to see what limits are actually being imposed.
Note that the XRGB1555 can be dropped from the g4x+ variant
since the plane no longer supports that format anyway.
TODO: maybe go for vfuncs later
v2: Update for lnl changes
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com> #v1
Reviewed-by: Vinod Govindapillai <vinod.govindapillai at intel.com> #v1
Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_fbc.c | 47 ++++++++++++++++++++++--
1 file changed, 43 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 8999ef3f0972..37f96a4d50f2 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -917,7 +917,7 @@ static bool stride_is_valid(const struct intel_plane_state *plane_state)
return i8xx_fbc_stride_is_valid(plane_state);
}
-static bool pixel_format_is_valid(const struct intel_plane_state *plane_state)
+static bool i8xx_fbc_pixel_format_is_valid(const struct intel_plane_state *plane_state)
{
struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
const struct drm_framebuffer *fb = plane_state->hw.fb;
@@ -931,20 +931,59 @@ static bool pixel_format_is_valid(const struct intel_plane_state *plane_state)
/* 16bpp not supported on gen2 */
if (DISPLAY_VER(i915) == 2)
return false;
+ return true;
+ default:
+ return false;
+ }
+}
+
+static bool g4x_fbc_pixel_format_is_valid(const struct intel_plane_state *plane_state)
+{
+ struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
+
+ switch (fb->format->format) {
+ case DRM_FORMAT_XRGB8888:
+ case DRM_FORMAT_XBGR8888:
+ return true;
+ case DRM_FORMAT_RGB565:
/* WaFbcOnly1to1Ratio:ctg */
if (IS_G4X(i915))
return false;
return true;
+ default:
+ return false;
+ }
+}
+
+static bool lnl_fbc_pixel_format_is_valid(const struct intel_plane_state *plane_state)
+{
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
+
+ switch (fb->format->format) {
+ case DRM_FORMAT_XRGB8888:
+ case DRM_FORMAT_XBGR8888:
case DRM_FORMAT_ARGB8888:
case DRM_FORMAT_ABGR8888:
- if (DISPLAY_VER(i915) >= 20)
- return true;
- fallthrough;
+ case DRM_FORMAT_RGB565:
+ return true;
default:
return false;
}
}
+static bool pixel_format_is_valid(const struct intel_plane_state *plane_state)
+{
+ struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
+
+ if (DISPLAY_VER(i915) >= 20)
+ return lnl_fbc_pixel_format_is_valid(plane_state);
+ else if (DISPLAY_VER(i915) >= 5 || IS_G4X(i915))
+ return g4x_fbc_pixel_format_is_valid(plane_state);
+ else
+ return i8xx_fbc_pixel_format_is_valid(plane_state);
+}
+
static bool i8xx_fbc_rotation_is_valid(const struct intel_plane_state *plane_state)
{
return plane_state->hw.rotation == DRM_MODE_ROTATE_0;
--
2.41.0
More information about the Intel-gfx
mailing list