[Intel-gfx] [PATCH 06/10] drm/i915/spi: spi register with mtd

[Usyskin, Alexander]

Hi Miquel, 

> > +static int i915_spi_init_mtd(struct i915_spi *spi, struct device *device,
> > +			     unsigned int nparts)
> > +{
> > +	unsigned int i;
> > +	unsigned int n;
> > +	struct mtd_partition *parts = NULL;
> > +	int ret;
> > +
> > +	dev_dbg(device, "registering with mtd\n");
> > +
> > +	spi->mtd.owner = THIS_MODULE;
> > +	spi->mtd.dev.parent = device;
> > +	spi->mtd.flags = MTD_CAP_NORFLASH | MTD_WRITEABLE;
> > +	spi->mtd.type = MTD_DATAFLASH;
> > +	spi->mtd.priv = spi;
> > +	spi->mtd._write = i915_spi_write;
> > +	spi->mtd._read = i915_spi_read;
> > +	spi->mtd._erase = i915_spi_erase;
> > +	spi->mtd._get_device = i915_spi_get_device;
> > +	spi->mtd._put_device = i915_spi_put_device;
> > +	spi->mtd.writesize = SZ_1; /* 1 byte granularity */
> 
> You say writesize should be aligned with 4 in your next patch?

We support unaligned write by reading aligned 4bytes,
replacing changed bytes there and writing whole 4bytes back.
Is there any problem with this approach?

> 
> > +	spi->mtd.erasesize = SZ_4K; /* 4K bytes granularity */
> > +	spi->mtd.size = spi->size;
> > +

-- 
Thanks,
Sasha