[Intel-gfx] [PATCH 06/10] drm/i915/spi: spi register with mtd

[Usyskin, Alexander]

> > > > +	spi->mtd.writesize = SZ_1; /* 1 byte granularity */
> > >
> > > You say writesize should be aligned with 4 in your next patch?
> >
> > We support unaligned write by reading aligned 4bytes,
> > replacing changed bytes there and writing whole 4bytes back.
> > Is there any problem with this approach?
> 
> Is there a reason to do that manually rather than letting the core
> handle the complexity?
> 
I was not aware that core can do this. The core implements above logic
if I put SZ_4 here and caller try to write, say, one byte?
And sync multiple writers?
If so, I can remove manual work, I think, and make the patches smaller.

-- 
Thanks,
Sasha