[Intel-gfx] [PATCH] drm/i915/mtl: Add Wa_14019821291

[Matt Roper]

On Wed, Oct 18, 2023 at 01:34:43PM +0530, Dnyaneshwar Bhadane wrote:
> This workaround is primarily implemented by the BIOS.  However if the
> BIOS applies the workaround it will reserve a small piece of our DSM
> (which should be at the top, right below the WOPCM); we just need to
> keep that region reserved so that nothing else attempts to re-use it.
> 
> Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane at intel.com>
> ---
>  drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 18 ++++++++++++++++++
>  drivers/gpu/drm/i915/i915_reg.h            |  2 ++
>  2 files changed, 20 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> index 1a766d8e7cce..b2bc5aab88d3 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> @@ -409,6 +409,24 @@ static void icl_get_stolen_reserved(struct drm_i915_private *i915,
>  		*base -= *size;
>  	else
>  		*base = reg_val & GEN11_STOLEN_RESERVED_ADDR_MASK;
> +
> +	/* Wa_14019821291*/
> +	if (IS_MEDIA_GT_IP_STEP(i915->media_gt, IP_VER(13, 0), STEP_A0, STEP_C0)) {

When I check the workaround database I don't see this going away on C0
stepping.  It's just listed as a permanent workaround that applies to
all steppings as far as I can see.  So just

        if (MEDIA_VER_FULL(i915) == IP_VER(13, 0))

should be sufficient.

> +		/*
> +		 * This workaround is primarily implemented by the BIOS.  We
> +		 * just need to figure out whether the BIOS has applied the
> +		 * workaround (meaning the programmed address falls within
> +		 * the DSM) and, if so, reserve that part of the DSM to
> +		 * prevent accidental reuse.  The DSM location should be just
> +		 * below the WOPCM.
> +		 */
> +
> +		u64 gscpsmi_base = intel_uncore_read64_2x32(uncore,
> +							    MTL_GSCPSMI_BASEADDR_LSB,
> +							    MTL_GSCPSMI_BASEADDR_MSB);
> +		if (gscpsmi_base >= *base && gscpsmi_base < *base + *size)
> +			*size = gscpsmi_base - *base;
> +	}
>  }
>  
>  /*
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 135e8d8dbdf0..31d0692a5620 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6399,5 +6399,7 @@ enum skl_power_gate {
>  #define   MTL_TRDPRE_MASK		REG_GENMASK(7, 0)
>  
>  #define MTL_MEDIA_GSI_BASE		0x380000
> +#define MTL_GSCPSMI_BASEADDR_LSB		_MMIO(MTL_MEDIA_GSI_BASE + 0x880c)
> +#define MTL_GSCPSMI_BASEADDR_MSB		_MMIO(MTL_MEDIA_GSI_BASE + 0x8810)

There's no need to manually add MTL_MEDIA_GSI_BASE into the register
offset; the intel_uncore_* functions take care of doing that
automatically when you read/write the register.  Just _MMIO(0x88xx) is
sufficient.

Also, since these are GT registers, they should probably be in
gt/intel_gt_regs.h instead of this header.


Matt

>  
>  #endif /* _I915_REG_H_ */
> -- 
> 2.34.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation