[Intel-gfx] [PATCH v2 22/24] drm/i915/display: Move nuclear_pageflip under display
Luca Coelho
luca at coelho.fi
Mon Oct 23 14:01:06 UTC 2023
On Mon, 2023-10-16 at 14:16 +0300, Jouni Högander wrote:
> Signed-off-by: Jouni Högander <jouni.hogander at intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display_device.c | 2 +-
> drivers/gpu/drm/i915/display/intel_display_params.c | 3 +++
> drivers/gpu/drm/i915/display/intel_display_params.h | 1 +
> drivers/gpu/drm/i915/i915_params.c | 3 ---
> drivers/gpu/drm/i915/i915_params.h | 1 -
> 5 files changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
> index 50841818fb59..0b522c6a8d6f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
> @@ -1113,7 +1113,7 @@ void intel_display_device_info_runtime_init(struct drm_i915_private *i915)
> }
>
> /* Disable nuclear pageflip by default on pre-g4x */
> - if (!i915->params.nuclear_pageflip &&
> + if (!i915->display.params.nuclear_pageflip &&
> DISPLAY_VER(i915) < 5 && !IS_G4X(i915))
> i915->drm.driver_features &= ~DRIVER_ATOMIC;
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c b/drivers/gpu/drm/i915/display/intel_display_params.c
> index e86766639396..3045a1b9b704 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_params.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_params.c
> @@ -90,6 +90,9 @@ intel_display_param_named(disable_display, bool, 0400,
> intel_display_param_named(verbose_state_checks, bool, 0400,
> "Enable verbose logs (ie. WARN_ON()) in case of unexpected hw state conditions.");
>
> +intel_display_param_named_unsafe(nuclear_pageflip, bool, 0400,
> + "Force enable atomic functionality on platforms that don't have full support yet.");
> +
> intel_display_param_named_unsafe(enable_fbc, int, 0400,
> "Enable frame buffer compression for power savings "
> "(default: -1 (use per-chip default))");
> diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h b/drivers/gpu/drm/i915/display/intel_display_params.h
> index b35443f51375..d25e17f88a78 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_params.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_params.h
> @@ -40,6 +40,7 @@ struct drm_i915_private;
> param(bool, force_reset_modeset_test, false, 0600) \
> param(bool, disable_display, false, 0400) \
> param(bool, verbose_state_checks, true, 0) \
> + param(bool, nuclear_pageflip, false, 0400) \
> param(int, enable_fbc, -1, 0600) \
> param(int, enable_psr, -1, 0600) \
> param(bool, psr_safest_params, false, 0400) \
> diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
> index 72614c139222..18424873442d 100644
> --- a/drivers/gpu/drm/i915/i915_params.c
> +++ b/drivers/gpu/drm/i915/i915_params.c
> @@ -93,9 +93,6 @@ i915_param_named(mmio_debug, int, 0400,
> "Enable the MMIO debug code for the first N failures (default: off). "
> "This may negatively affect performance.");
>
> -i915_param_named_unsafe(nuclear_pageflip, bool, 0400,
> - "Force enable atomic functionality on platforms that don't have full support yet.");
> -
> i915_param_named_unsafe(enable_guc, int, 0400,
> "Enable GuC load for GuC submission and/or HuC load. "
> "Required functionality can be selected using bitmask values. "
> diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
> index 4b543beb17ca..c7fff571db2c 100644
> --- a/drivers/gpu/drm/i915/i915_params.h
> +++ b/drivers/gpu/drm/i915/i915_params.h
> @@ -64,7 +64,6 @@ struct drm_printer;
> /* leave bools at the end to not create holes */ \
> param(bool, enable_hangcheck, true, 0600) \
> param(bool, error_capture, true, IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) ? 0600 : 0) \
> - param(bool, nuclear_pageflip, false, 0400) \
> param(bool, enable_dp_mst, true, 0600) \
> param(bool, enable_gvt, false, IS_ENABLED(CONFIG_DRM_I915_GVT) ? 0400 : 0)
>
Reviewed-by: Luca Coelho <luciano.coelho at intel.com>
--
Cheers,
Luca.
More information about the Intel-gfx
mailing list