[Intel-gfx] [PATCH 00/12] drm/i915: VRR, LRR, and M/N stuff

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala at linux.intel.com>

Attempt to make VRR, LRR, and M/N updates coexist nicely,
allowing fastsets whenever feasible.

Lightly smoke tested on my adl.

Cc: Manasi Navare <navaremanasi at chromium.org>                                                                         

Ville Syrjälä (12):
  drm/i915: Move psr unlock out from the pipe update critical section
  drm/i915: Change intel_pipe_update_{start,end}() calling convention
  drm/i915: Extract intel_crtc_vblank_evade_scanlines()
  drm/i915: Enable VRR later during fastsets
  drm/i915: Adjust seamless_m_n flag behaviour
  drm/i915: Optimize out redundant M/N updates
  drm/i915: Relocate is_in_vrr_range()
  drm/i915: Validate that the timings are within the VRR range
  drm/i915: Disable VRR during seamless M/N changes
  drm/i915: Update VRR parameters in fastset
  drm/i915: Assert that VRR is off during vblank evasion if necessary
  drm/i915: Implement transcoder LRR for TGL+

 drivers/gpu/drm/i915/display/intel_atomic.c   |   2 +
 drivers/gpu/drm/i915/display/intel_crtc.c     | 110 ++++++++------
 drivers/gpu/drm/i915/display/intel_crtc.h     |   6 +-
 drivers/gpu/drm/i915/display/intel_display.c  | 135 ++++++++++++++----
 .../drm/i915/display/intel_display_device.h   |   1 +
 .../drm/i915/display/intel_display_types.h    |   5 +-
 drivers/gpu/drm/i915/display/intel_dp.c       |   2 +-
 drivers/gpu/drm/i915/display/intel_panel.c    |  17 +--
 drivers/gpu/drm/i915/display/intel_vrr.c      |  18 ++-
 drivers/gpu/drm/i915/display/intel_vrr.h      |   1 +
 drivers/gpu/drm/i915/i915_reg.h               |   1 +
 11 files changed, 212 insertions(+), 86 deletions(-)

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2.41.0