[Intel-gfx] [PATCH v4] drm/i915: Added Wa_18022495364

[Matt Roper]

On Mon, Sep 11, 2023 at 05:19:33PM +0530, Dnyaneshwar Bhadane wrote:
> This workaround has two different implementations,
> one for gen 12 to DG2 and another for DG2 and later.

Since this workaround is no longer relevant to any platforms DG2 or
later, I think we can drop the mention of those.

> In this patch only GEN12 changes are implemented.
> BSpec: 11354
> 
> v2:
> - Removed extra parentheses from the condition (Lucas)
> - Fixed spacing and new line (Lucas)
> 
> v3:
> - Fixed commit message.
> 
> v4:
> - Only GEN12 changes are kept(Matt Ropper)
> - Renamed the register bit in define
> 
> Cc: Lucas De Marchi <lucas.demarchi at intel.com>
> Cc: Matt Roper <matthew.d.roper at intel.com>
> Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane at intel.com>
> Reviewed-by: Nemesa Garg <nemesa.garg at intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_gt_regs.h     | 2 ++
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 ++++
>  2 files changed, 6 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 0e4c638fcbbf..38f02ef8ed01 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -164,6 +164,8 @@
>  #define GEN9_CSFE_CHICKEN1_RCS			_MMIO(0x20d4)
>  #define   GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE	(1 << 2)
>  #define   GEN11_ENABLE_32_PLANE_MODE		(1 << 7)
> +#define GEN12_CS_DEBUG_MODE2			_MMIO(0x20d8)
> +#define   INSTRUCTION_STATE_CACHE_INVALIDATE	REG_BIT(6)
>  
>  #define GEN7_FF_SLICE_CS_CHICKEN1		_MMIO(0x20e0)
>  #define   GEN9_FFSC_PERCTX_PREEMPT_CTRL		(1 << 14)
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 864d41bcf6bb..30aca8d03f6b 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -712,6 +712,10 @@ static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine,
>  			    GEN9_PREEMPT_GPGPU_LEVEL_MASK,
>  			    GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL);
>  
> +	/* Wa_18022495364 */
> +	wa_masked_en(wal, GEN12_CS_DEBUG_MODE2,
> +		     INSTRUCTION_STATE_CACHE_INVALIDATE);

The formal text for this workaround seemed a bit vague/ambiguous so I
had to go back and read some of the background in the workaround
database to figure out whether this is actually what they were asking us
to do or not.  Unfortunately it doesn't sound like this is what they had
in mind; what you have here how we'd generally apply a register setting
as part of the initial "golden context" at initialization.  The golden
context would be copied to create the starting context for each new GPU
client, and this value would then be properly saved/restored as part of
the context image on each context switch thereafter.

However this workaround is a bit unusual since this isn't just a
register setting that they want initialized a certain way and preserved
thereafter.  Instead, this specific register bit has an immediate side
effect (invalidating a GPU cache) at the specific point it is written.
The goal of this workaround is to actually perform an explicit
invalidation of that cache (by re-writing the register) during every GPU
context switch, which is accomplished via a "workaround batchbuffer"
that's attached to the context via INDIRECT_CTX.

We already have general setup/handling for INDIRECT_CTX-based
workarounds in the driver, although it's a bit different from the
"usual" workarounds that we deal with 99% of the time.  In this case you
want to add a GPU instruction (MI_LOAD_REGISTER_IMM) to the batchbuffer
that's being generated inside gen12_emit_indirect_ctx_rcs() of
drivers/gpu/drm/i915/gt/intel_lrc.c (you should probably make a new
function in that file and call it from gen12_emit_indirect_ctx_rcs).
What you need to do would be very similar to what we're already doing in
dg2_emit_draw_watermark_setting, just with a different register/value.


Matt

> +
>  	/*
>  	 * Wa_16011163337 - GS_TIMER
>  	 *
> -- 
> 2.34.1

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation