[Intel-gfx] [PATCH] drm/i915/irq: Clear GFX_MSTR_IRQ as part of IRQ reset

[Gustavo Sousa]

Quoting Gustavo Sousa (2023-09-19 14:49:53-03:00)
>Starting with Xe_LP+, GFX_MSTR_IRQ contains status bits that have W1C
>behavior. If we do not properly reset them, we would miss delivery of
>interrupts if a pending bit is set when enabling IRQs.
>
>As an example, the display part of our probe routine contains paths
>where we wait for vblank interrupts. If a display interrupt was already
>pending when enabling IRQs, we would time out waiting for the vblank.
>
>Avoid the potential issue by clearing GFX_MSTR_IRQ as part of the IRQ
>reset.
>
>BSpec: 50875, 54028
>Signed-off-by: Gustavo Sousa <gustavo.sousa at intel.com>

FYI: This is the i915 version of
https://patchwork.freedesktop.org/series/123920/ .

Gustavo Sousa

>---
> drivers/gpu/drm/i915/gt/intel_gt_irq.c | 3 +++
> 1 file changed, 3 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
>index 77fb57223465..849dea61fc74 100644
>--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
>+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
>@@ -214,6 +214,9 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
> {
>         struct intel_uncore *uncore = gt->uncore;
> 
>+        if (gt->type != GT_MEDIA && GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 10))
>+                intel_uncore_write(uncore, GEN11_GFX_MSTR_IRQ, ~0);
>+
>         /* Disable RCS, BCS, VCS and VECS class engines. */
>         intel_uncore_write(uncore, GEN11_RENDER_COPY_INTR_ENABLE, 0);
>         intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE,          0);
>-- 
>2.42.0
>