[Intel-gfx] [PATCH v3 17/25] drm/i915/dp_mst: Fix PBN calculation with FEC overhead

[Imre Deak]

On Wed, Sep 20, 2023 at 01:58:43PM +0300, Ville Syrjälä wrote:
> On Thu, Sep 14, 2023 at 10:26:51PM +0300, Imre Deak wrote:
> > On 8b/10b MST links the PBN value for DSC streams must be calculated
> > accounting for the FEC overhead. The same applies to 8b/10b non-DSC
> > streams if there is another DSC stream on the same link. Fix up the PBN
> > calculation accordingly.
> > 
> > Signed-off-by: Imre Deak <imre.deak at intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 ++-
> >  1 file changed, 2 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > index 01291bbb44693..c1fea894d3774 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > @@ -110,7 +110,8 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
> >  
> >  		crtc_state->pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock,
> >  						       bpp << 4,
> > -						       false);
> > +						       (dsc || crtc_state->fec_enable) &&
> > +							!intel_dp_is_uhbr(crtc_state));
> 
> Why is this not simply 'fec_enable'?

For DSC it's enabled only after the link configuration is computed. I
can move that enabling from intel_dp_dsc_compute_config() earlier
instead.

> >  
> >  		slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst_mgr,
> >  						      connector->port,
> > -- 
> > 2.37.2
> 
> -- 
> Ville Syrjälä
> Intel