[Intel-gfx] [PATCH] drm/i915: Add Wa_18028616096

[Gustavo Sousa]

Quoting Shekhar Chauhan (2023-09-20 01:05:47-03:00)
>Drop UGM per set fragment threshold to 3
>
>BSpec: 54833
>Signed-off-by: Shekhar Chauhan <shekhar.chauhan at intel.com>
>---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h     | 1 +
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++
> 2 files changed, 4 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>index a00ff51c681d..f8ab99affa15 100644
>--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>@@ -1227,6 +1227,7 @@
> #define EU_PERF_CNTL3                                PERF_REG(0xe758)
> 
> #define LSC_CHICKEN_BIT_0                        MCR_REG(0xe7c8)
>+#define   UGM_FRAGMENT_THRESHOLD_TO_3                REG_BIT(58)

You probably want to define this as:

  #define   UGM_FRAGMENT_THRESHOLD_TO_3                REG_BIT(58 - 32)

, and after the definition of LSC_CHICKEN_BIT_0_UDW.

See more below...

> #define   DISABLE_D8_D16_COASLESCE                REG_BIT(30)
> #define   FORCE_1_SUB_MESSAGE_PER_FRAGMENT        REG_BIT(15)
> #define LSC_CHICKEN_BIT_0_UDW                        MCR_REG(0xe7c8 + 4)
>diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>index 660d4f358eab..3f3977014ee7 100644
>--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>@@ -2914,6 +2914,9 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
>                  * Wa_22015475538:dg2
>                  */
>                 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8);
>+
>+                /* Wa_18028616096:dg2 */
>+                wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, UGM_FRAGMENT_THRESHOLD_TO_3);

...and here, use LSC_CHICKEN_BIT_0_UDW as target.

--
Gustavo Sousa

>         }
> 
>         if (IS_DG2_G11(i915)) {
>-- 
>2.34.1
>