[Intel-gfx] [PATCH v4 2/2] drm/i915/lnl: FBC is supported with per pixel alpha

[Govindapillai, Vinod]

On Wed, 2023-09-13 at 13:38 +0300, Ville Syrjälä wrote:
> On Mon, Sep 04, 2023 at 02:55:17PM +0300, Vinod Govindapillai wrote:
> > For LNL onwards, FBC can be supported on planes with per
> > pixel alpha
> > 
> > Bspec: 69560
> > Signed-off-by: Vinod Govindapillai <vinod.govindapillai at intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_fbc.c | 3 ++-
> >  1 file changed, 2 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> > index a3999ad95a19..c0e4caec03ea 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > @@ -1209,7 +1209,8 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state,
> >                 return 0;
> >         }
> >  
> > -       if (plane_state->hw.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE &&
> > +       if (DISPLAY_VER(i915) < 20 &&
> 
> Bspec still says 15. Someone needs to figure this mess out for
> all LNL patches.
> 
> > +           plane_state->hw.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE &&
> >             fb->format->has_alpha) {
> 
> We would have already rejected the pixel format earlier, so atm this
> check is redundant.

Hi,

Could you please clarify this.

This is an existing check and I just added to limit this versions before 20.
As we have this FBC possibility to plane 0/1/2, isn't this restriction not applied to any of those
planes as well. 

Though at the moment there is no possibility to set FBC any one of this possibility explicitly, we
plan to have some IGT cases where we would like to validate this feature by having cases with only 0
or 1 or 2 plane and check FBC is enablement is okay.

BR
Vinod

> 
> >                 plane_state->no_fbc_reason = "per-pixel alpha not supported";
> >                 return 0;
> > -- 
> > 2.34.1
>