[Intel-gfx] [PATCH] drm/i915: Don't set PIPE_CONTROL_FLUSH_L3 for aux inval

[Tapani Pälli]

Fixes all regressions we saw, I also run some extra vulkan and GL 
workloads, no regressions observed.

Tested-by: Tapani Pälli <tapani.palli at intel.com>

On 26.9.2023 17.24, Nirmoy Das wrote:
> PIPE_CONTROL_FLUSH_L3 is not needed for aux invalidation
> so don't set that.
>
> Fixes: 78a6ccd65fa3 ("drm/i915/gt: Ensure memory quiesced before invalidation")
> Cc: Jonathan Cavitt <jonathan.cavitt at intel.com>
> Cc: Andi Shyti <andi.shyti at linux.intel.com>
> Cc: <stable at vger.kernel.org> # v5.8+
> Cc: Andrzej Hajda <andrzej.hajda at intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
> Cc: Matt Roper <matthew.d.roper at intel.com>
> Cc: Tejas Upadhyay <tejas.upadhyay at intel.com>
> Cc: Lucas De Marchi <lucas.demarchi at intel.com>
> Cc: Prathap Kumar Valsan <prathap.kumar.valsan at intel.com>
> Cc: Tapani Pälli <tapani.palli at intel.com>
> Cc: Mark Janes <mark.janes at intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi at intel.com>
> Signed-off-by: Nirmoy Das <nirmoy.das at intel.com>
> ---
>   drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 11 ++++++++++-
>   1 file changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> index 0143445dba83..ba4c2422b340 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> @@ -271,8 +271,17 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
>   		if (GRAPHICS_VER_FULL(rq->i915) >= IP_VER(12, 70))
>   			bit_group_0 |= PIPE_CONTROL_CCS_FLUSH;
>   
> +		/*
> +		 * L3 fabric flush is needed for AUX CCS invalidation
> +		 * which happens as part of pipe-control so we can
> +		 * ignore PIPE_CONTROL_FLUSH_L3. Also PIPE_CONTROL_FLUSH_L3
> +		 * deals with Protected Memory which is not needed for
> +		 * AUX CCS invalidation and lead to unwanted side effects.
> +		 */
> +		if (mode & EMIT_FLUSH)
> +			bit_group_1 |= PIPE_CONTROL_FLUSH_L3;
> +
>   		bit_group_1 |= PIPE_CONTROL_TILE_CACHE_FLUSH;
> -		bit_group_1 |= PIPE_CONTROL_FLUSH_L3;
>   		bit_group_1 |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
>   		bit_group_1 |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
>   		/* Wa_1409600907:tgl,adl-p */