[Intel-gfx] [PATCH] drm/i915/mtl: Update workaround 14016712196

[Tvrtko Ursulin]

On 12/09/2023 13:46, Rodrigo Vivi wrote:
> On Mon, Aug 28, 2023 at 12:04:50PM +0530, Tejas Upadhyay wrote:
>> Now this workaround is permanent workaround on MTL and DG2,
> 
> since this also impacts DG2, the subject 'drm/i915/mtl'
> is wrong. I know, this is water under the bridge now.


Found this while writing the 6.7 pull request as I was assessing 
individual patches.

Indeed, patch subject is wrong, but function name mtl_dummy_pipe_control 
is also now wrong. Probably just change the prefix to gen12.

Tejas, can you please send a follow up patch to tidy this up.

Regards,

Tvrtko

> Another thing is this patch doesn't apply clean on drm-intel-fixes
> because it depends on 5a213086a025 ("drm/i915: Eliminate IS_MTL_GRAPHICS_STEP")
> that also doesn't apply cleanly so I'm not cherry-picking them.
> 
> If this patch is critical for a stable 6.6, please provide a backported
> version on top of drm-intel-fixes. You don't need to send the patch,
> just respond to this email pointing to a branch with the patch is enough.
> 
> Thanks,
> Rodrigo.
> 
>> earlier we used to apply on MTL A0 step only.
>> VLK-45480
>>
>> Fixes: d922b80b1010 ("drm/i915/gt: Add workaround 14016712196")
>> Signed-off-by: Tejas Upadhyay <tejas.upadhyay at intel.com>
>> ---
>>   drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 7 +++----
>>   1 file changed, 3 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>> index 6187b25b67ab..0143445dba83 100644
>> --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>> +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>> @@ -226,8 +226,8 @@ u32 *gen12_emit_aux_table_inv(struct intel_engine_cs *engine, u32 *cs)
>>   static int mtl_dummy_pipe_control(struct i915_request *rq)
>>   {
>>   	/* Wa_14016712196 */
>> -	if (IS_GFX_GT_IP_STEP(rq->engine->gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
>> -	    IS_GFX_GT_IP_STEP(rq->engine->gt, IP_VER(12, 71), STEP_A0, STEP_B0)) {
>> +	if (IS_GFX_GT_IP_RANGE(rq->engine->gt, IP_VER(12, 70), IP_VER(12, 71)) ||
>> +	    IS_DG2(rq->i915)) {
>>   		u32 *cs;
>>   
>>   		/* dummy PIPE_CONTROL + depth flush */
>> @@ -810,8 +810,7 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
>>   		     PIPE_CONTROL_FLUSH_ENABLE);
>>   
>>   	/* Wa_14016712196 */
>> -	if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
>> -	    IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))
>> +	if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)) || IS_DG2(i915))
>>   		/* dummy PIPE_CONTROL + depth flush */
>>   		cs = gen12_emit_pipe_control(cs, 0,
>>   					     PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0);
>> -- 
>> 2.25.1
>>