[PATCH 0/8] drm/i915: BXT/GLK per-lane vswing and PHY reg cleanup

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala at linux.intel.com>

Start off with a bit of cleanup around the BXT/GLK DPIO
PHY registers, and finish off with per-lane vswing
programming.

Ville Syrjälä (8):
  drm/i915/dpio: Clean up bxt/glk PHY registers
  drm/i915/dpio: Add per-lane PHY TX register definitons for bxt/glk
  drm/i915/dpio: Extract bxt_dpio_phy_regs.h
  drm/i915/dpio: Introdude bxt_ddi_phy_rmw_grp()
  drm/i915/dpio: Use intel_de_rmw() for BXT DPIO latency optim setup
  drm/i915/dpio: s/ddi/dpio/ for bxt/glk PHY stuff
  drm/i915/dpio: Program bxt/glk PHY TX registers per-lane
  drm/i915: Enable per-lane DP drive settings for bxt/glk

 .../gpu/drm/i915/display/bxt_dpio_phy_regs.h  | 273 ++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_ddi.c      |  10 +-
 .../i915/display/intel_display_power_well.c   |  18 +-
 .../drm/i915/display/intel_dp_link_training.c |   2 +-
 drivers/gpu/drm/i915/display/intel_dp_mst.c   |   2 +-
 drivers/gpu/drm/i915/display/intel_dpio_phy.c | 213 ++++++++------
 drivers/gpu/drm/i915/display/intel_dpio_phy.h |  48 +--
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c |   3 +-
 drivers/gpu/drm/i915/i915_reg.h               | 262 -----------------
 9 files changed, 432 insertions(+), 399 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/bxt_dpio_phy_regs.h

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2.43.2