✗ Fi.CI.CHECKPATCH: warning for drm/i915: PLL refactoring

[Patchwork]

== Series Details ==

Series: drm/i915: PLL refactoring
URL   : https://patchwork.freedesktop.org/series/132392/
State : warning

== Summary ==

Error: dim checkpatch failed
14bdc0367571 drm/i915: Replace hand rolled PLL state dump with intel_dpll_dump_hw_state()
c07ae2c34376 drm/i915: Use printer for the rest of PLL debugfs dump
6bddd5b19e86 drm/i915: Rename PLL hw_state variables/arguments
-:345: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#345: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:2852:
+		hw_state->div0 = TGL_DPLL0_DIV0_AFC_STARTUP(i915->display.vbt.override_afc_startup_val);

total: 0 errors, 1 warnings, 0 checks, 604 lines checked
cc06bcedebfb drm/i915: Introduce some local PLL state variables
556a7d6a2bd1 drm/i915: Extract ilk_fb_cb_factor()
ec8d5fca4aca drm/i915: Extract ilk_dpll_compute_fp()
c98904ae3912 drm/i915: Extract i9xx_dpll_get_hw_state()
b71270cf5abf drm/i915: Pass the PLL hw_state to pll->enable()
38c9026555e2 drm/i915: Extract i965_dpll_md()
ae27779441b1 drm/i915: Extract {i9xx,i8xx,ilk}_dpll()
c673e5a40815 drm/i915: Inline {i9xx,ilk}_update_pll_dividers()
a113d7ae2667 drm/i915: Modernize i9xx_pll_refclk()
edf028ec40c2 drm/i915: Drop pointless 'crtc' argument from *_crtc_clock_get()
1e12b7a384c9 drm/i915: s/pipe_config/crtc_state/ in legacy PLL code
560a05be0d68 drm/i915: Add local DPLL 'hw_state' variables
00fd678e3c41 drm/i915: Carve up struct intel_dpll_hw_state
e4b09211a12c drm/i915: Unionize dpll_hw_state
780e3fc506c5 drm/i915: Suck snps/cx0 PLL states into dpll_hw_state
-:119: WARNING:LONG_LINE: line length of 114 exceeds 100 columns
#119: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:4015:
+		crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll);

-:130: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#130: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:4025:
+	crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->dpll_hw_state.mpllb);

-:211: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#211: FILE: drivers/gpu/drm/i915/display/intel_dpll.c:1225:
+	crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll);

total: 0 errors, 3 warnings, 0 checks, 239 lines checked