✗ Fi.CI.CHECKPATCH: warning for Enable display support for Battlemage

[Patchwork]

== Series Details ==

Series: Enable display support for Battlemage
URL   : https://patchwork.freedesktop.org/series/132429/
State : warning

== Summary ==

Error: dim checkpatch failed
7b481503a16a drm/xe/display: Lane reversal requires writes to both context lanes
9846f194e976 drm/i915/display: Enable RM timeout detection
d2d6861c4a95 drm/i915/bmg: Define IS_BATTLEMAGE macro
-:35: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'i915' may be better as '(i915)' to avoid precedence issues
#35: FILE: drivers/gpu/drm/i915/i915_drv.h:545:
+#define IS_LUNARLAKE(i915) (0 && i915)

-:36: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'i915' may be better as '(i915)' to avoid precedence issues
#36: FILE: drivers/gpu/drm/i915/i915_drv.h:546:
+#define IS_BATTLEMAGE(i915)  (0 && i915)

total: 0 errors, 0 warnings, 2 checks, 16 lines checked
f21722e5a1a3 drm/i915/xe2hpd: Skip CCS modifiers
-:10: WARNING:TYPO_SPELLING: 'auxillary' may be misspelled - perhaps 'auxiliary'?
#10: 
auxillary surface in the plane, containing the CCS data.  But on
^^^^^^^^^

-:12: WARNING:TYPO_SPELLING: 'auxillary' may be misspelled - perhaps 'auxiliary'?
#12: 
part of the plane. It contains no auxillary surface.
                                  ^^^^^^^^^

-:41: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#41: FILE: drivers/gpu/drm/i915/display/intel_fb.c:435:
+	if (intel_fb_is_ccs_modifier(md->modifier)) {
+

total: 0 errors, 2 warnings, 1 checks, 22 lines checked
ddb2038eff98 drm/i915/xe2hpd: Initial cdclk table
5f7384cf9619 drm/i915/bmg: Extend DG2 tc check to future
996917ef9a77 drm/i915/xe2hpd: Properly disable power in port A
9670370a984c drm/i915/xe2hpd: Add new C20 PHY SRAM address
-:78: WARNING:LONG_LINE: line length of 109 exceeds 100 columns
#78: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2201:
+									  PHY_C20_B_MPLLB_CNTX_CFG(i915, i));

-:84: WARNING:LONG_LINE: line length of 109 exceeds 100 columns
#84: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2205:
+									  PHY_C20_A_MPLLB_CNTX_CFG(i915, i));

-:94: WARNING:LONG_LINE: line length of 109 exceeds 100 columns
#94: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2213:
+									  PHY_C20_B_MPLLA_CNTX_CFG(i915, i));

-:100: WARNING:LONG_LINE: line length of 109 exceeds 100 columns
#100: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2217:
+									  PHY_C20_A_MPLLA_CNTX_CFG(i915, i));

total: 0 errors, 4 warnings, 0 checks, 203 lines checked
cc9949785238 drm/i915/xe2hpd: Add support for eDP PLL configuration
907b8baf0534 drm/i915/xe2hpd: update pll values in sync with Bspec
-:13: ERROR:BAD_SIGN_OFF: Unrecognized email address: 'Matt Roper <matthew.d.roper at intel.com'
#13: 
Reviewed-by: Matt Roper <matthew.d.roper at intel.com

total: 1 errors, 0 warnings, 0 checks, 63 lines checked
4a77891392e1 drm/i915/xe2hpd: Add display info
679e3e1fe907 drm/i915/xe2hpd: Configure CHICKEN_MISC_2 before enabling planes
65f214fabdb1 drm/i915/xe2hpd: Add max memory bandwidth algorithm
588ecac64872 drm/i915/xe2hpd: Do not program MBUS_DBOX BW credits
9ab2a09e8c47 drm/i915/bmg: BMG should re-use MTL's south display logic
db96fdf0fd8e Revert "drm/i915/dgfx: DGFX uses direct VBT pin mapping"
8b55113d20b9 drm/i915/xe2hpd: Set maximum DP rate to UHBR13.5
ff9b3247174f drm/xe/gt_print: add xe_gt_err_once()
fa62a2f06462 drm/xe/device: implement transient flush
e3f4d7dd775d drm/i915/display: perform transient flush
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 6, in <module>
    from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 6, in <module>
    from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
-:58: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#58: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 76 lines checked
f50365fa323c drm/xe/bmg: Enable the display support