[PATCH 2/2] drm/i915/pps: Disable DPLS_GATING around pps sequence

[Bhadane, Dnyaneshwar]

> -----Original Message-----
> From: Kandpal, Suraj <suraj.kandpal at intel.com>
> Sent: Tuesday, April 16, 2024 12:58 PM
> To: intel-gfx at lists.freedesktop.org
> Cc: Borah, Chaitanya Kumar <chaitanya.kumar.borah at intel.com>; Shankar,
> Uma <uma.shankar at intel.com>; Nautiyal, Ankit K
> <ankit.k.nautiyal at intel.com>; Bhadane, Dnyaneshwar
> <dnyaneshwar.bhadane at intel.com>; Kandpal, Suraj
> <suraj.kandpal at intel.com>
> Subject: [PATCH 2/2] drm/i915/pps: Disable DPLS_GATING around pps
> sequence
> 
> Disable bit 29 of SCLKGATE_DIS register around pps sequence when we turn
> panel power on.
> WA: 16023567976
> Bspec: 49304
> 
> Signed-off-by: Suraj Kandpal <suraj.kandpal at intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_pps.c | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
> b/drivers/gpu/drm/i915/display/intel_pps.c
> index 3078dfac7817..a912e712ca63 100644
> --- a/drivers/gpu/drm/i915/display/intel_pps.c
> +++ b/drivers/gpu/drm/i915/display/intel_pps.c
> @@ -919,6 +919,7 @@ void intel_pps_on_unlocked(struct intel_dp
> *intel_dp)
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>  	u32 pp;
>  	i915_reg_t pp_ctrl_reg;
> +	int dis_ver = DISPLAY_VER(dev_priv);
> 
>  	lockdep_assert_held(&dev_priv->display.pps.mutex);
> 
> @@ -948,6 +949,13 @@ void intel_pps_on_unlocked(struct intel_dp
> *intel_dp)
>  		intel_de_posting_read(dev_priv, pp_ctrl_reg);
>  	}
> 
> +	/* WA: 16023567976
> +	 * Disable DPLS gating around power sequence.
> +	 */
> +	if (dis_ver >= 12 && dis_ver <= 14)
Hi Suraj,
You might want to use IS_DISPLAY_IP_RANGE() as it is fixed IP based range.

Dnyaneshwar
> +		intel_de_rmw(dev_priv, SCLKGATE_DIS,
> +			     DPLS_GATING_DISABLE, 1);
> +
>  	pp |= PANEL_POWER_ON;
>  	if (!IS_IRONLAKE(dev_priv))
>  		pp |= PANEL_POWER_RESET;
> @@ -958,6 +966,10 @@ void intel_pps_on_unlocked(struct intel_dp
> *intel_dp)
>  	wait_panel_on(intel_dp);
>  	intel_dp->pps.last_power_on = jiffies;
> 
> +	if (dis_ver >= 12 && dis_ver <= 14)
> +		intel_de_rmw(dev_priv, SCLKGATE_DIS,
> +			     DPLS_GATING_DISABLE, 0);
> +
>  	if (IS_IRONLAKE(dev_priv)) {
>  		pp |= PANEL_POWER_RESET; /* restore panel reset bit */
>  		intel_de_write(dev_priv, pp_ctrl_reg, pp);
> --
> 2.43.2