[PATCH v3 18/19] drm/i915/display: perform transient flush

[Lucas De Marchi]

+Jani

On Tue, Apr 30, 2024 at 10:28:49AM GMT, Radhakrishna Sripada wrote:
>From: Matthew Auld <matthew.auld at intel.com>
>
>Perform manual transient cache flush prior to flip and at the end of
>frontbuffer_flush. This is needed to ensure display engine doesn't see
>garbage if the surface is L3:XD dirty.
>
>Testcase: igt at xe-pat@display-vs-wb-transient
>Signed-off-by: Matthew Auld <matthew.auld at intel.com>
>Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan at intel.com>
>Acked-by: Nirmoy Das <nirmoy.das at intel.com>
>Reviewed-by: Matt Roper <matthew.d.roper at intel.com>
>Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada at intel.com>
>---
> drivers/gpu/drm/i915/display/intel_display.c  |  3 +++
> .../gpu/drm/i915/display/intel_frontbuffer.c  |  2 ++
> drivers/gpu/drm/i915/display/intel_tdf.h      | 25 +++++++++++++++++++
> drivers/gpu/drm/xe/Makefile                   |  3 ++-
> drivers/gpu/drm/xe/display/xe_tdf.c           | 13 ++++++++++
> 5 files changed, 45 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/i915/display/intel_tdf.h
> create mode 100644 drivers/gpu/drm/xe/display/xe_tdf.c
>
>diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>index 00e583fc2a8c..294539b4ca99 100644
>--- a/drivers/gpu/drm/i915/display/intel_display.c
>+++ b/drivers/gpu/drm/i915/display/intel_display.c
>@@ -109,6 +109,7 @@
> #include "intel_sdvo.h"
> #include "intel_snps_phy.h"
> #include "intel_tc.h"
>+#include "intel_tdf.h"
> #include "intel_tv.h"
> #include "intel_vblank.h"
> #include "intel_vdsc.h"
>@@ -7225,6 +7226,8 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>
> 	intel_atomic_commit_fence_wait(state);
>
>+	intel_td_flush(dev_priv);
>+
> 	drm_atomic_helper_wait_for_dependencies(&state->base);
> 	drm_dp_mst_atomic_wait_for_dependencies(&state->base);
> 	intel_atomic_global_state_wait_for_dependencies(state);
>diff --git a/drivers/gpu/drm/i915/display/intel_frontbuffer.c b/drivers/gpu/drm/i915/display/intel_frontbuffer.c
>index 2ea37c0414a9..4923c340a0b6 100644
>--- a/drivers/gpu/drm/i915/display/intel_frontbuffer.c
>+++ b/drivers/gpu/drm/i915/display/intel_frontbuffer.c
>@@ -65,6 +65,7 @@
> #include "intel_fbc.h"
> #include "intel_frontbuffer.h"
> #include "intel_psr.h"
>+#include "intel_tdf.h"
>
> /**
>  * frontbuffer_flush - flush frontbuffer
>@@ -93,6 +94,7 @@ static void frontbuffer_flush(struct drm_i915_private *i915,
> 	trace_intel_frontbuffer_flush(i915, frontbuffer_bits, origin);
>
> 	might_sleep();
>+	intel_td_flush(i915);
> 	intel_drrs_flush(i915, frontbuffer_bits);
> 	intel_psr_flush(i915, frontbuffer_bits, origin);
> 	intel_fbc_flush(i915, frontbuffer_bits, origin);
>diff --git a/drivers/gpu/drm/i915/display/intel_tdf.h b/drivers/gpu/drm/i915/display/intel_tdf.h
>new file mode 100644
>index 000000000000..353cde21f6c2
>--- /dev/null
>+++ b/drivers/gpu/drm/i915/display/intel_tdf.h
>@@ -0,0 +1,25 @@
>+/* SPDX-License-Identifier: MIT */
>+/*
>+ * Copyright © 2024 Intel Corporation
>+ */
>+
>+#ifndef __INTEL_TDF_H__
>+#define __INTEL_TDF_H__
>+
>+/*
>+ * TDF (Transient-Data-Flush) is needed for Xe2+ where special L3:XD caching can
>+ * be enabled through various PAT index modes. Idea is to use this caching mode
>+ * when for example rendering onto the display surface, with the promise that
>+ * KMD will ensure transient cache entries are always flushed by the time we do
>+ * the display flip, since display engine is never coherent with CPU/GPU caches.
>+ */
>+
>+struct drm_i915_private;
>+
>+#ifdef I915
>+static inline void intel_td_flush(struct drm_i915_private *i915) {}
>+#else
>+void intel_td_flush(struct drm_i915_private *i915);
>+#endif
>+
>+#endif
>diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
>index a67977edff5b..b620389761d5 100644
>--- a/drivers/gpu/drm/xe/Makefile
>+++ b/drivers/gpu/drm/xe/Makefile
>@@ -206,7 +206,8 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
> 	display/xe_dsb_buffer.o \
> 	display/xe_fb_pin.o \
> 	display/xe_hdcp_gsc.o \
>-	display/xe_plane_initial.o
>+	display/xe_plane_initial.o \
>+	display/xe_tdf.o
>
> # SOC code shared with i915
> xe-$(CONFIG_DRM_XE_DISPLAY) += \
>diff --git a/drivers/gpu/drm/xe/display/xe_tdf.c b/drivers/gpu/drm/xe/display/xe_tdf.c
>new file mode 100644
>index 000000000000..2c0d4e144e09
>--- /dev/null
>+++ b/drivers/gpu/drm/xe/display/xe_tdf.c
>@@ -0,0 +1,13 @@
>+// SPDX-License-Identifier: MIT
>+/*
>+ * Copyright © 2024 Intel Corporation
>+ */
>+
>+#include "xe_device.h"
>+#include "intel_display_types.h"
>+#include "intel_tdf.h"
>+
>+void intel_td_flush(struct drm_i915_private *i915)
>+{
>+	xe_device_td_flush(i915);

this would be the display side "calling back onto xe". I think it's ok
given the current status quo, but Cc'ing Jani.

This also needs the previous 2 patches, which I'm ok with merging
through drm-intel-next if this user here is the correct way to
implement.

Lucas De Marchi

>+}
>-- 
>2.34.1
>