[PATCH v3 10/21] drm/i915/psr: Rename has_psr2 as has_sel_update

Manna, Animesh animesh.manna at intel.com
Fri Feb 2 11:22:27 UTC 2024



> -----Original Message-----
> From: Hogander, Jouni <jouni.hogander at intel.com>
> Sent: Friday, January 19, 2024 3:40 PM
> To: intel-gfx at lists.freedesktop.org
> Cc: Manna, Animesh <animesh.manna at intel.com>; Hogander, Jouni
> <jouni.hogander at intel.com>
> Subject: [PATCH v3 10/21] drm/i915/psr: Rename has_psr2 as
> has_sel_update
> 
> We are going to reuse has_psr2 for panel_replay as well. Rename it as
> has_sel_update to avoid confusion.
> 
> v2: Rebase
> 
> Signed-off-by: Jouni Högander <jouni.hogander at intel.com>

Reviewed-by: Animesh Manna <animesh.manna at intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_crtc_state_dump.c |  5 +++--
>  drivers/gpu/drm/i915/display/intel_display.c         |  2 +-
>  drivers/gpu/drm/i915/display/intel_display_types.h   |  2 +-
>  drivers/gpu/drm/i915/display/intel_dp.c              |  2 +-
>  drivers/gpu/drm/i915/display/intel_fbc.c             |  2 +-
>  drivers/gpu/drm/i915/display/intel_psr.c             | 10 +++++-----
>  6 files changed, 12 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> index 49fd100ec98a..5edbc9b3d766 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> @@ -266,9 +266,10 @@ void intel_crtc_state_dump(const struct
> intel_crtc_state *pipe_config,
>  		drm_dbg_kms(&i915->drm, "sdp split: %s\n",
>  			    str_enabled_disabled(pipe_config-
> >sdp_split_enable));
> 
> -		drm_dbg_kms(&i915->drm, "psr: %s, psr2: %s, panel replay:
> %s, selective fetch: %s\n",
> +		drm_dbg_kms(&i915->drm,
> +			    "psr: %s, selective update: %s, panel replay: %s,
> selective
> +fetch: %s\n",
>  			    str_enabled_disabled(pipe_config->has_psr),
> -			    str_enabled_disabled(pipe_config->has_psr2),
> +			    str_enabled_disabled(pipe_config-
> >has_sel_update),
>  			    str_enabled_disabled(pipe_config-
> >has_panel_replay),
>  			    str_enabled_disabled(pipe_config-
> >enable_psr2_sel_fetch));
>  	}
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index b7e5b2774f2e..8bf1ba30b3fc 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5220,7 +5220,7 @@ intel_pipe_config_compare(const struct
> intel_crtc_state *current_config,
>  	 */
>  	if (current_config->has_panel_replay || pipe_config-
> >has_panel_replay) {
>  		PIPE_CONF_CHECK_BOOL(has_psr);
> -		PIPE_CONF_CHECK_BOOL(has_psr2);
> +		PIPE_CONF_CHECK_BOOL(has_sel_update);
>  		PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
>  		PIPE_CONF_CHECK_BOOL(enable_psr2_su_region_et);
>  		PIPE_CONF_CHECK_BOOL(has_panel_replay);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index ae2e8cff9d69..5890fef86547 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1211,7 +1211,7 @@ struct intel_crtc_state {
> 
>  	/* PSR is supported but might not be enabled due the lack of enabled
> planes */
>  	bool has_psr;
> -	bool has_psr2;
> +	bool has_sel_update;
>  	bool enable_psr2_sel_fetch;
>  	bool enable_psr2_su_region_et;
>  	bool req_psr2_sdp_prior_scanline;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 11143fb9b0f0..4e01182662ff 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2633,7 +2633,7 @@ static void intel_dp_compute_vsc_sdp(struct
> intel_dp *intel_dp,
>  	if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
>  		intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
>  						 vsc);
> -	} else if (crtc_state->has_psr2) {
> +	} else if (crtc_state->has_psr && crtc_state->has_sel_update) {
>  		/*
>  		 * [PSR2 without colorimetry]
>  		 * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index f17a1afb4929..647dd1b56073 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -1235,7 +1235,7 @@ static int intel_fbc_check_plane(struct
> intel_atomic_state *state,
>  	 * Recommendation is to keep this combination disabled
>  	 * Bspec: 50422 HSD: 14010260002
>  	 */
> -	if (IS_DISPLAY_VER(i915, 12, 14) && crtc_state->has_psr2) {
> +	if (IS_DISPLAY_VER(i915, 12, 14) && crtc_state->has_sel_update) {
>  		plane_state->no_fbc_reason = "PSR2 enabled";
>  		return 0;
>  	}
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 24a80f47b84f..e328bef8916f 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -651,7 +651,7 @@ void intel_psr_enable_sink(struct intel_dp *intel_dp,
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>  	u8 dpcd_val = DP_PSR_ENABLE;
> 
> -	if (crtc_state->has_psr2) {
> +	if (crtc_state->has_sel_update) {
>  		/* Enable ALPM at sink for psr2 */
>  		if (!crtc_state->has_panel_replay)
>  			drm_dp_dpcd_writeb(&intel_dp->aux,
> @@ -1433,7 +1433,7 @@ void intel_psr_compute_config(struct intel_dp
> *intel_dp,
>  	if (!crtc_state->has_psr)
>  		return;
> 
> -	crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state);
> +	crtc_state->has_sel_update = intel_psr2_config_valid(intel_dp,
> +crtc_state);
>  }
> 
>  void intel_psr_get_config(struct intel_encoder *encoder, @@ -1466,7
> +1466,7 @@ void intel_psr_get_config(struct intel_encoder *encoder,
>  		pipe_config->has_psr = true;
>  	}
> 
> -	pipe_config->has_psr2 = intel_dp->psr.psr2_enabled;
> +	pipe_config->has_sel_update = intel_dp->psr.psr2_enabled;
>  	pipe_config->infoframes.enable |=
> intel_hdmi_infoframe_enable(DP_SDP_VSC);
> 
>  	if (!intel_dp->psr.psr2_enabled)
> @@ -1691,7 +1691,7 @@ static void intel_psr_enable_locked(struct intel_dp
> *intel_dp,
> 
>  	drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled);
> 
> -	intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
> +	intel_dp->psr.psr2_enabled = crtc_state->has_sel_update;
>  	intel_dp->psr.panel_replay_enabled = crtc_state->has_panel_replay;
>  	intel_dp->psr.busy_frontbuffer_bits = 0;
>  	intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
> @@ -2368,7 +2368,7 @@ void intel_psr_pre_plane_update(struct
> intel_atomic_state *state,
>  		needs_to_disable |=
> intel_crtc_needs_modeset(new_crtc_state);
>  		needs_to_disable |= !new_crtc_state->has_psr;
>  		needs_to_disable |= !new_crtc_state->active_planes;
> -		needs_to_disable |= new_crtc_state->has_psr2 != psr-
> >psr2_enabled;
> +		needs_to_disable |= new_crtc_state->has_sel_update !=
> +psr->psr2_enabled;
>  		needs_to_disable |= DISPLAY_VER(i915) < 11 &&
>  			new_crtc_state->wm_level_disabled;
> 
> --
> 2.34.1



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