✗ Fi.CI.CHECKPATCH: warning for drm/i915/dsc: Fix the macro that calculates DSCC_/DSCA_ PPS reg address (rev2)
Patchwork
patchwork at emeril.freedesktop.org
Mon Feb 5 21:16:54 UTC 2024
== Series Details ==
Series: drm/i915/dsc: Fix the macro that calculates DSCC_/DSCA_ PPS reg address (rev2)
URL : https://patchwork.freedesktop.org/series/129486/
State : warning
== Summary ==
Error: dim checkpatch failed
6a38025388cc drm/i915/dsc: Fix the macro that calculates DSCC_/DSCA_ PPS reg address
-:7: WARNING:COMMIT_LOG_LONG_LINE: Prefer a maximum 75 chars per line (possible unwrapped commit description?)
#7:
Commit bd077259d0a9 ("drm/i915/vdsc: Add function to read any PPS register") defines
-:45: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#45: FILE: drivers/gpu/drm/i915/display/intel_vdsc_regs.h:54:
+#define DSCA_PPS(pps) _MMIO(_DSCA_PPS_0 + ((pps) < 12 ? (pps):(pps) + 12) * 4)
-:45: CHECK:SPACING: spaces required around that ':' (ctx:VxV)
#45: FILE: drivers/gpu/drm/i915/display/intel_vdsc_regs.h:54:
+#define DSCA_PPS(pps) _MMIO(_DSCA_PPS_0 + ((pps) < 12 ? (pps):(pps) + 12) * 4)
^
-:45: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pps' - possible side-effects?
#45: FILE: drivers/gpu/drm/i915/display/intel_vdsc_regs.h:54:
+#define DSCA_PPS(pps) _MMIO(_DSCA_PPS_0 + ((pps) < 12 ? (pps):(pps) + 12) * 4)
-:46: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#46: FILE: drivers/gpu/drm/i915/display/intel_vdsc_regs.h:55:
+#define DSCC_PPS(pps) _MMIO(_DSCC_PPS_0 + ((pps) < 12 ? (pps):(pps) + 12) * 4)
-:46: CHECK:SPACING: spaces required around that ':' (ctx:VxV)
#46: FILE: drivers/gpu/drm/i915/display/intel_vdsc_regs.h:55:
+#define DSCC_PPS(pps) _MMIO(_DSCC_PPS_0 + ((pps) < 12 ? (pps):(pps) + 12) * 4)
^
-:46: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pps' - possible side-effects?
#46: FILE: drivers/gpu/drm/i915/display/intel_vdsc_regs.h:55:
+#define DSCC_PPS(pps) _MMIO(_DSCC_PPS_0 + ((pps) < 12 ? (pps):(pps) + 12) * 4)
total: 0 errors, 3 warnings, 4 checks, 10 lines checked
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