[PATCH v2] drm/i915/panelreplay: Panel replay workaround with VRR
Animesh Manna
animesh.manna at intel.com
Fri Feb 9 15:43:00 UTC 2024
Panel Replay VSC SDP not getting sent when VRR is enabled
and W1 and W2 are 0. So Program Set Context Latency in
TRANS_SET_CONTEXT_LATENCY register to at least a value of 1.
HSD: 14015406119
v1: Initial version.
v2: Update timings stored in adjusted_mode struct. [Ville]
Signed-off-by: Animesh Manna <animesh.manna at intel.com>
---
drivers/gpu/drm/i915/display/intel_vblank.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
index baf7354cb6e2..2e11629e4e9f 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.c
+++ b/drivers/gpu/drm/i915/display/intel_vblank.c
@@ -552,6 +552,19 @@ void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state,
adjusted_mode.crtc_vtotal = crtc_state->vrr.vmax;
adjusted_mode.crtc_vblank_end = crtc_state->vrr.vmax;
adjusted_mode.crtc_vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
+
+ /*
+ * WA: HSD-14015406119
+ * Program Set Context Latency in TRANS_SET_CONTEXT_LATENCY register
+ * to at least a value of 1 when Panel Replay is enabled with VRR.
+ * Value for TRANS_SET_CONTEXT_LATENCY is calculated by substracting
+ * crtc_vdisplay from crtc_vblank_start, so incrementing crtc_vblank_start
+ * by 1 if both are equal.
+ */
+ if (DISPLAY_VER(i915) >= 13 && crtc_state->has_panel_replay &&
+ adjusted_mode.crtc_vblank_start == adjusted_mode.crtc_vdisplay)
+ adjusted_mode.crtc_vblank_start += 1;
+
vmax_vblank_start = intel_vrr_vmax_vblank_start(crtc_state);
} else {
mode_flags &= ~I915_MODE_FLAG_VRR;
--
2.29.0
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