[PATCH 00/28] Plane Color Pipeline support for Intel platforms

[Pekka Paalanen]

On Tue, 13 Feb 2024 12:18:07 +0530
Uma Shankar <uma.shankar at intel.com> wrote:

> This series intends to add support for Plane Color Management for
> Intel platforms. This is based on the design which has been agreed
> upon by the community. Series implementing the design for generic
> DRM core has been sent out by Harry Wentland and is under review
> below:
> https://patchwork.freedesktop.org/series/123446/
> 
> The base work of above series is squashed under 1 patch and support
> for Intel platform is added on top of it.
> Any reviews on the original core design is expected to be done in 
> Harry's series to avoid any forking of the discussion.
> 
> We have added some changes/fixes to the Harry's core DRM changes,
> being put up as separate patches on top of squashed patch. These are
> expected to get included in the main series from Harry once agreed upon.
> 
> Changes added on core design:
> 1. Below patches implement some fixes on original series
> drm: Add missing function declarations
> drm: handle NULL next colorop in drm_colorop_set_next_property
> drm: Fix error logging in set Color Pipeline
> 
> 2. Implemented a HW capability property to expose segmented luts.
> drm: Add Color lut range attributes
> drm: Add Color ops capability property
> drm: Define helper to create color ops capability property
> drm: Define helper for adding capability property for 1D LUT
> 
> This helps in generically defining the hardware lut capabilities,
> lut distribution, precision, segmented or PWL LUTS.
> 
> 3. Added support for enhanced prescision, 3x3 matrix and 1d LUT:
> drm: Add Enhanced LUT precision structure
> drm: Add support for 3x3 CTM
> drm: Add 1D LUT color op
> 
> On top of this base work for DRM core plane color pipeline design,
> implementation is done for Intel hardware platforms. Below patches
> include the same:
> 
> drm/i915: Add identifiers for intel color blocks
> drm/i915: Add intel_color_op
> drm/i915/color: Add helper to allocate intel colorop
> drm/i915/color: Add helper to create intel colorop
> drm/i915/color: Create a transfer function color pipeline
> drm/i915/color: Add and attach COLORPIPELINE plane property
> drm/i915/color: Add framework to set colorop
> drm/i915/color: Add callbacks to set plane CTM
> drm/i915/color: Add framework to program PRE/POST CSC LUT
> FIXME: force disable legacy plane color properties for TGL and beyond
> drm/i915/color: Enable Plane Color Pipelines
> drm/i915: Define segmented Lut and add capabilities to colorop
> drm/i915/color: Add plane CTM callback for TGL and beyond
> drm/i915: Add register definitions for Plane Degamma
> drm/i915: Add register definitions for Plane Post CSC
> drm/i915/color: Program Pre-CSC registers
> drm/i915/xelpd: Program Plane Post CSC Registers
> 
> Bhanu from Intel will be sending out the igt changes to help test the
> color pipeline implementation based on the current igt changes sent out
> by Harry.
> https://patchwork.freedesktop.org/series/123448/
> 
> Planned Next Steps:
> 1. Work with Harry and community and get DRM core changes for color
> pipeline merged.
> 2. Implement pipe color management (post blending) based on the current
> color pipeline design.
> 3. Work with compositor maintainers to get color processing implemented
> using display hardware, thereby avoid any GL or GPU shaders.
> 
> Thanks to all the community maintainers and contributors who have helped
> to get this support in upstream Linux. Looking forward to collaborate,
> work together and get this merged.
> 

...

> Chaitanya Kumar Borah (16):
>   drm: Add missing function declarations
>   drm: handle NULL next colorop in drm_colorop_set_next_property
>   drm: Fix error logging in set Color Pipeline
>   drm: Add support for 3x3 CTM
>   drm: Add 1D LUT color op
>   drm/i915: Add identifiers for intel color blocks
>   drm/i915: Add intel_color_op
>   drm/i915/color: Add helper to allocate intel colorop
>   drm/i915/color: Add helper to create intel colorop
>   drm/i915/color: Create a transfer function color pipeline
>   drm/i915/color: Add and attach COLORPIPELINE plane property
>   drm/i915/color: Add framework to set colorop
>   drm/i915/color: Add callbacks to set plane CTM
>   drm/i915/color: Add framework to program PRE/POST CSC LUT
>   FIXME: force disable legacy plane color properties for TGL and beyond
>   drm/i915/color: Enable Plane Color Pipelines
> 
> Harry Wentland (1):
>   [NOT FOR REVIEW] drm: color pipeline base work
> 
> Uma Shankar (11):
>   drm: Add Enhanced LUT precision structure
>   drm: Add Color lut range attributes
>   drm: Add Color ops capability property
>   drm: Define helper to create color ops capability property
>   drm: Define helper for adding capability property for 1D LUT
>   drm/i915: Define segmented Lut and add capabilities to colorop
>   drm/i915/color: Add plane CTM callback for TGL and beyond
>   drm/i915: Add register definitions for Plane Degamma
>   drm/i915: Add register definitions for Plane Post CSC
>   drm/i915/color: Program Pre-CSC registers
>   drm/i915/xelpd: Program Plane Post CSC Registers


Hi Uma,

it is really hard for me to get a good picture of what this would result
in from userspace perspective, which properties will exist with what
values, but I didn't spot any fundamental UAPI design problems so far.


Thanks,
pq
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