[PATCH 6/6] drm/i915/display: Read/Write AS sdp only when sink/source has enabled
Nautiyal, Ankit K
ankit.k.nautiyal at intel.com
Tue Feb 20 06:37:37 UTC 2024
On 2/16/2024 7:50 PM, Mitul Golani wrote:
> Write/Read Adaptive sync SDP only when Sink and Source is enabled
> for the same. Also along with write TRANS_VRR_VSYNC values.
>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani at intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 4 ++++
> .../gpu/drm/i915/display/intel_display_device.h | 1 +
> drivers/gpu/drm/i915/display/intel_dp.c | 15 +++++++++++++++
> drivers/gpu/drm/i915/display/intel_dp.h | 1 +
> drivers/gpu/drm/i915/display/intel_vrr.c | 7 +++++++
> 5 files changed, 28 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index bea441590204..68cd49193d03 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3926,6 +3926,7 @@ static void intel_ddi_get_config(struct intel_encoder *encoder,
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
> + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>
> /* XXX: DSI transcoder paranoia */
> if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)))
> @@ -3972,6 +3973,9 @@ static void intel_ddi_get_config(struct intel_encoder *encoder,
> intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA);
> intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
>
> + if (HAS_AS_SDP(dev_priv) && intel_dp_sink_as_sdp_supported(intel_dp))
> + intel_read_dp_sdp(encoder, pipe_config, DP_SDP_ADAPTIVE_SYNC);
> +
> intel_audio_codec_get_config(encoder, pipe_config);
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
> index fe4268813786..6399fbc6c738 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> @@ -68,6 +68,7 @@ struct drm_printer;
> #define HAS_TRANSCODER(i915, trans) ((DISPLAY_RUNTIME_INFO(i915)->cpu_transcoder_mask & \
> BIT(trans)) != 0)
> #define HAS_VRR(i915) (DISPLAY_VER(i915) >= 11)
> +#define HAS_AS_SDP(i915) (DISPLAY_VER(i915) >= 13)
> #define INTEL_NUM_PIPES(i915) (hweight8(DISPLAY_RUNTIME_INFO(i915)->pipe_mask))
> #define I915_HAS_HOTPLUG(i915) (DISPLAY_INFO(i915)->has_hotplug)
> #define OVERLAY_NEEDS_PHYSICAL(i915) (DISPLAY_INFO(i915)->overlay_needs_physical)
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 0759266e7bfb..5bd99fa8f200 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -119,6 +119,17 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
> return dig_port->base.type == INTEL_OUTPUT_EDP;
> }
>
> +bool
> +intel_dp_sink_as_sdp_supported(struct intel_dp *intel_dp)
> +{
> + u8 dpcd[DP_RECEIVER_CAP_SIZE];
> +
> + if (drm_dp_read_dpcd_caps(&intel_dp->aux, dpcd))
> + return -EIO;
> +
This is already read in intel_dp->dpcd, we can use that.
> + return drm_dp_as_sdp_supported(&intel_dp->aux, dpcd);
> +}
> +
> static void intel_dp_unset_edid(struct intel_dp *intel_dp);
>
> /* Is link rate UHBR and thus 128b/132b? */
> @@ -4330,6 +4341,7 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder,
> VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK |
> VIDEO_DIP_ENABLE_ADAPTIVE_SYNC;
> u32 val = intel_de_read(dev_priv, reg) & ~dip_enable;
> + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>
> /* TODO: Sanitize DSC enabling wrt. intel_dsc_dp_pps_write(). */
> if (!enable && HAS_DSC(dev_priv))
> @@ -4347,6 +4359,9 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder,
>
> intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
>
> + if (HAS_AS_SDP(dev_priv) && intel_dp_sink_as_sdp_supported(intel_dp))
> + intel_write_dp_sdp(encoder, crtc_state, DP_SDP_ADAPTIVE_SYNC);
> +
> intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> index 530cc97bc42f..09ab313af896 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -180,5 +180,6 @@ intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
> struct link_config_limits *limits);
>
> void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_connector *connector);
> +bool intel_dp_sink_as_sdp_supported(struct intel_dp *intel_dp);
>
> #endif /* __INTEL_DP_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 2fa0004d00c7..86729e145991 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -192,6 +192,9 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> + bool is_as_sdp_enabled = intel_de_read(dev_priv,
> + HSW_TVIDEO_DIP_CTL(cpu_transcoder)) &
> + VIDEO_DIP_ENABLE_ADAPTIVE_SYNC;
>
> /*
> * TRANS_SET_CONTEXT_LATENCY with VRR enabled
> @@ -210,6 +213,10 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
> intel_de_write(dev_priv, TRANS_VRR_VMAX(cpu_transcoder), crtc_state->vrr.vmax - 1);
> intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), trans_vrr_ctl(crtc_state));
> intel_de_write(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder), crtc_state->vrr.flipline - 1);
> +
> + if (is_as_sdp_enabled)
As mentioned in Patch#4, lets use the crtc_state->vrr.as_sdp_enable,
instead of this.
Regards,
Ankit
> + intel_de_write(dev_priv, TRANS_VRR_VSYNC(cpu_transcoder),
> + crtc_state->vrr.vsync_end << 16 | crtc_state->vrr.vsync_start);
> }
>
> void intel_vrr_send_push(const struct intel_crtc_state *crtc_state)
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