[PATCH] drm/i915: Fix doc build issue on intel_cdclk.c

[Rodrigo Vivi]

Fixing some doc build issues:

Documentation/gpu/i915:222: drivers/gpu/drm/i915/display/intel_cdclk.c:69: ERROR: Unexpected indentation.
Documentation/gpu/i915:222: ./drivers/gpu/drm/i915/display/intel_cdclk.c:70: WARNING: Block quote ends without a blank line; unexpected unindent.

Closes: https://lore.kernel.org/all/20240219161747.0e867406@canb.auug.org.au/
Fixes: 79e2ea2eaaa6 ("drm/i915/cdclk: Document CDCLK update methods")
Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
Cc: Gustavo Sousa <gustavo.sousa at intel.com>
Reported-by: Stephen Rothwell <sfr at canb.auug.org.au>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 30dae4fef6cb..42cbc3203d2c 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -65,13 +65,19 @@
  *
  * Several methods exist to change the CDCLK frequency, which ones are
  * supported depends on the platform:
+ *
  * - Full PLL disable + re-enable with new VCO frequency. Pipes must be inactive.
+ *
  * - CD2X divider update. Single pipe can be active as the divider update
  *   can be synchronized with the pipe's start of vblank.
+ *
  * - Crawl the PLL smoothly to the new VCO frequency. Pipes can be active.
+ *
  * - Squash waveform update. Pipes can be active.
+ *
  * - Crawl and squash can also be done back to back. Pipes can be active.
  *
+ *
  * RAWCLK is a fixed frequency clock, often used by various auxiliary
  * blocks such as AUX CH or backlight PWM. Hence the only thing we
  * really need to know about RAWCLK is its frequency so that various
-- 
2.43.2