[PATCH v2 00/21] drm/i915: Add Display Port tunnel BW allocation support
Maxime Ripard
mripard at kernel.org
Mon Feb 26 13:59:52 UTC 2024
On Mon, Feb 26, 2024 at 03:54:19PM +0200, Jani Nikula wrote:
> On Tue, 20 Feb 2024, Imre Deak <imre.deak at intel.com> wrote:
> > This is v2 of [1], with the following changes:
> >
> > - Several functional/typo/formatting fixes, detailed in the patches.
> > - Move the BW allocation from encoder hooks to
> > intel_atomic_commit_tail() fixing the allocation for MST streams
> > enabled/disabled w/o a full modeset (i.e. w/o re-enabling the master
> > stream).
> > - Fix an MST mode restore issue during system resume, which also lead
> > to a tunnel BW allocation failure. (Patch 3)
> > - Ensure a DPCD DPRX cap read as required by the TBT CM any time a long
> > HPD pulse is detected. (Patch 20)
> > - Explicitly disable the BW allocation mode during system suspend.
> >
> > The patchset is also available at:
> > https://github.com/ideak/linux/commits/dp_tun_bw_alloc
> >
> > Cc: Mika Westerberg <mika.westerberg at linux.intel.com>
> > Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
> > Cc: Uma Shankar <uma.shankar at intel.com>
> > Cc: Jouni Högander <jouni.hogander at intel.com>
> > Cc: Saranya Gopal <saranya.gopal at intel.com>
> > Cc: Rajaram Regupathy <rajaram.regupathy at intel.com>
> > Cc: Gil Fine <gil.fine at intel.com>
> > Cc: Naama Shachar <naamax.shachar at intel.com>
> > Cc: Pengfei Xu <pengfei.xu at intel.com>
> >
> > [1] https://lore.kernel.org/all/20240123102850.390126-1-imre.deak@intel.com
> >
> > Imre Deak (21):
> > drm/dp: Add drm_dp_max_dprx_data_rate()
> > drm/dp: Add support for DP tunneling
>
> Maarten, Maxime, Thomas -
>
> Ack for merging these two patches via drm-intel-next?
Yep, go ahead
Maxime
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 228 bytes
Desc: not available
URL: <https://lists.freedesktop.org/archives/intel-gfx/attachments/20240226/771fcaa3/attachment.sig>
More information about the Intel-gfx
mailing list