[PATCH] drm/i915/display/dp: 128/132b DP-capable with SST

[Nautiyal, Ankit K]

On 1/3/2024 2:37 PM, Arun R Murthy wrote:
> With a value of '0' read from MSTM_CAP register MST to be enabled.
> DP2.1 SCR updates the spec for 128/132b DP capable supporting only one
> stream and not supporting single stream sideband MSG.

I think, we still need to read bit DP_SINGLE_STREAM_SIDEBAND_MSG for 
single stream sideband capability.

Only if the MST_CAP is 1 we can ignore the DP_SINGLE_STREAM_SIDEBAND_MSG.

> The underlying protocol will be MST to enable use of MTP.
>
> Signed-off-by: Arun R Murthy <arun.r.murthy at intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_dp.c | 9 +++++++--
>   1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 9ff0cbd9c0df..40d3280f8d98 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -4038,8 +4038,13 @@ intel_dp_configure_mst(struct intel_dp *intel_dp)
>   	if (!intel_dp_mst_source_support(intel_dp))
>   		return;
>   
> -	intel_dp->is_mst = sink_can_mst &&
> -		i915->display.params.enable_dp_mst;
> +	/*
> +	 * Even if dpcd reg MSTM_CAP is 0, if the sink supports UHBR rates then
> +	 * DP2.1 can be enabled with underlying protocol using MST for MTP
> +	 */

I am not able to find this in the spec, am I missing anything here? If 
MST_CAP [Bit 0]  is 0, for both 8b/10b and 128b/132b, it says it does 
not support Multi stream Transport.

Regards,

Ankit


> +	intel_dp->is_mst = (sink_can_mst ||
> +			    drm_dp_is_uhbr_rate(intel_dp_max_common_rate(intel_dp)))
> +			    && i915->display.params.enable_dp_mst;
>   
>   	drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
>   					intel_dp->is_mst);