[PATCH 4/7] drm/i915/psr: Calculate and configure CUR_POS_ERLY_TPT

[Kahola, Mika]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces at lists.freedesktop.org> On Behalf Of Jouni Högander
> Sent: Monday, December 18, 2023 7:50 PM
> To: intel-gfx at lists.freedesktop.org
> Subject: [PATCH 4/7] drm/i915/psr: Calculate and configure CUR_POS_ERLY_TPT
> 
> New register CUR_POS_ERLY_TPT related to early transport is supposed to be configured when early transport is in use.
> 
> This register is used to configure cursor vertical postion from beginning of selective update area.
> 
> Bspec: 68927
> 

Reviewed-by: Mika Kahola <mika.kahola at intel.com>

> Signed-off-by: Jouni Högander <jouni.hogander at intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cursor.c | 32 ++++++++++++++++-----
>  drivers/gpu/drm/i915/i915_reg.h             |  2 ++
>  2 files changed, 27 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
> index 926e2de00eb5..ecff90e233f0 100644
> --- a/drivers/gpu/drm/i915/display/intel_cursor.c
> +++ b/drivers/gpu/drm/i915/display/intel_cursor.c
> @@ -47,12 +47,23 @@ static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
>  	return base + plane_state->view.color_plane[0].offset;
>  }
> 
> -static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
> +static u32 intel_cursor_position(const struct intel_crtc_state *crtc_state,
> +				 const struct intel_plane_state *plane_state,
> +				 bool early_tpt)
>  {
>  	int x = plane_state->uapi.dst.x1;
>  	int y = plane_state->uapi.dst.y1;
>  	u32 pos = 0;
> 
> +	/*
> +	 * Formula from Bspec:
> +	 * MAX(-1 * <Cursor vertical size from CUR_CTL base on cursor mode
> +	 * select setting> + 1, CUR_POS Y Position - Update region Y position
> +	 */
> +	if (early_tpt)
> +		y = max(-1 * drm_rect_height(&plane_state->uapi.dst) + 1,
> +			y - crtc_state->psr2_su_area.y1);
> +
>  	if (x < 0) {
>  		pos |= CURSOR_POS_X_SIGN;
>  		x = -x;
> @@ -274,7 +285,7 @@ static void i845_cursor_update_arm(struct intel_plane *plane,
>  		size = CURSOR_HEIGHT(height) | CURSOR_WIDTH(width);
> 
>  		base = intel_cursor_base(plane_state);
> -		pos = intel_cursor_position(plane_state);
> +		pos = intel_cursor_position(crtc_state, plane_state, false);
>  	}
> 
>  	/* On these chipsets we can only modify the base/size/stride @@ -503,17 +514,24 @@ static void
> i9xx_cursor_update_sel_fetch_arm(struct intel_plane *plane,
>  					     const struct intel_crtc_state *crtc_state,
>  					     const struct intel_plane_state *plane_state)  {
> -	struct drm_i915_private *i915 = to_i915(plane->base.dev);
> +	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
>  	enum pipe pipe = plane->pipe;
> 
>  	if (!crtc_state->enable_psr2_sel_fetch)
>  		return;
> 
> -	if (drm_rect_height(&plane_state->psr2_sel_fetch_area) > 0)
> -		intel_de_write_fw(i915, PLANE_SEL_FETCH_CTL(pipe, plane->id),
> +	if (drm_rect_height(&plane_state->psr2_sel_fetch_area) > 0) {
> +		if (crtc_state->enable_psr2_su_region_et) {
> +			u32 val = intel_cursor_position(crtc_state, plane_state,
> +				true);
> +			intel_de_write_fw(dev_priv, CURPOS_ERLY_TPT(pipe), val);
> +		}
> +
> +		intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id),
>  				  plane_state->ctl);
> -	else
> +	} else {
>  		i9xx_cursor_disable_sel_fetch_arm(plane, crtc_state);
> +	}
>  }
> 
>  /* TODO: split into noarm+arm pair */
> @@ -536,7 +554,7 @@ static void i9xx_cursor_update_arm(struct intel_plane *plane,
>  			fbc_ctl = CUR_FBC_EN | CUR_FBC_HEIGHT(height - 1);
> 
>  		base = intel_cursor_base(plane_state);
> -		pos = intel_cursor_position(plane_state);
> +		pos = intel_cursor_position(crtc_state, plane_state, false);
>  	}
> 
>  	/*
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 27dc903f0553..d6f7e68ba308 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3059,6 +3059,7 @@
>  #define   MCURSOR_MODE_64_ARGB_AX	(0x20 | MCURSOR_MODE_64_32B_AX)
>  #define _CURABASE		0x70084
>  #define _CURAPOS		0x70088
> +#define _CURAPOS_ERLY_TPT	0x7008c
>  #define   CURSOR_POS_Y_SIGN		REG_BIT(31)
>  #define   CURSOR_POS_Y_MASK		REG_GENMASK(30, 16)
>  #define   CURSOR_POS_Y(y)		REG_FIELD_PREP(CURSOR_POS_Y_MASK, (y))
> @@ -3087,6 +3088,7 @@
>  #define CURCNTR(pipe) _MMIO_CURSOR2(pipe, _CURACNTR)  #define CURBASE(pipe) _MMIO_CURSOR2(pipe, _CURABASE)
> #define CURPOS(pipe) _MMIO_CURSOR2(pipe, _CURAPOS)
> +#define CURPOS_ERLY_TPT(pipe) _MMIO_CURSOR2(pipe, _CURAPOS_ERLY_TPT)
>  #define CURSIZE(pipe) _MMIO_CURSOR2(pipe, _CURASIZE)  #define CUR_FBC_CTL(pipe) _MMIO_CURSOR2(pipe,
> _CUR_FBC_CTL_A)  #define CUR_CHICKEN(pipe) _MMIO_CURSOR2(pipe, _CUR_CHICKEN_A)
> --
> 2.34.1