[PATCH 6/7] drm/i915/psr: Enable psr2 early transport as possible

[Kahola, Mika]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces at lists.freedesktop.org> On Behalf Of Jouni Högander
> Sent: Monday, December 18, 2023 7:50 PM
> To: intel-gfx at lists.freedesktop.org
> Subject: [PATCH 6/7] drm/i915/psr: Enable psr2 early transport as possible
> 
> Check source and sink support for psr2 early transport and enable it if not disabled by debug flag.
> 
> Bspec: 68934
> 

Reviewed-by: Mika Kahola <mika.kahola at intel.com>

> Signed-off-by: Jouni Högander <jouni.hogander at intel.com>
> ---
>  .../drm/i915/display/intel_display_types.h    | 16 ++++++++------
>  drivers/gpu/drm/i915/display/intel_psr.c      | 22 ++++++++++++++++++-
>  drivers/gpu/drm/i915/display/intel_psr_regs.h |  1 +
>  3 files changed, 31 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 05dd8decd610..ca8bc909ea35 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1215,6 +1215,7 @@ struct intel_crtc_state {
>  	bool has_psr;
>  	bool has_psr2;
>  	bool enable_psr2_sel_fetch;
> +	bool enable_psr2_su_region_et;
>  	bool req_psr2_sdp_prior_scanline;
>  	bool has_panel_replay;
>  	bool wm_level_disabled;
> @@ -1686,13 +1687,14 @@ struct intel_psr {
>  	/* Mutex for PSR state of the transcoder */
>  	struct mutex lock;
> 
> -#define I915_PSR_DEBUG_MODE_MASK	0x0f
> -#define I915_PSR_DEBUG_DEFAULT		0x00
> -#define I915_PSR_DEBUG_DISABLE		0x01
> -#define I915_PSR_DEBUG_ENABLE		0x02
> -#define I915_PSR_DEBUG_FORCE_PSR1	0x03
> -#define I915_PSR_DEBUG_ENABLE_SEL_FETCH	0x4
> -#define I915_PSR_DEBUG_IRQ		0x10
> +#define I915_PSR_DEBUG_MODE_MASK		0x0f
> +#define I915_PSR_DEBUG_DEFAULT			0x00
> +#define I915_PSR_DEBUG_DISABLE			0x01
> +#define I915_PSR_DEBUG_ENABLE			0x02
> +#define I915_PSR_DEBUG_FORCE_PSR1		0x03
> +#define I915_PSR_DEBUG_ENABLE_SEL_FETCH		0x4
> +#define I915_PSR_DEBUG_IRQ			0x10
> +#define I915_PSR_DEBUG_SU_REGION_ET_DISABLE	0x20
> 
>  	u32 debug;
>  	bool sink_support;
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 67f68c26a312..c29fd708608a 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -528,7 +528,7 @@ static void _psr_init_dpcd(struct intel_dp *intel_dp)
>  		intel_dp_get_sink_sync_latency(intel_dp);
> 
>  	if (DISPLAY_VER(i915) >= 9 &&
> -	    intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED) {
> +	    intel_dp->psr_dpcd[0] >= DP_PSR2_WITH_Y_COORD_IS_SUPPORTED) {
>  		bool y_req = intel_dp->psr_dpcd[1] &
>  			     DP_PSR2_SU_Y_COORDINATE_REQUIRED;
>  		bool alpm = intel_dp_get_alpm_status(intel_dp);
> @@ -604,6 +604,18 @@ static void hsw_psr_setup_aux(struct intel_dp *intel_dp)
>  		       aux_ctl);
>  }
> 
> +static bool psr2_su_region_et_valid(struct intel_dp *intel_dp) {
> +	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> +
> +	if (DISPLAY_VER(i915) >= 20 &&
> +	    intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED &&
> +	    !(intel_dp->psr.debug & I915_PSR_DEBUG_SU_REGION_ET_DISABLE))
> +		return true;
> +
> +	return false;
> +}
> +
>  static void intel_psr_enable_sink(struct intel_dp *intel_dp)  {
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); @@ -619,6 +631,8 @@ static void
> intel_psr_enable_sink(struct intel_dp *intel_dp)
>  				   DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE);
> 
>  		dpcd_val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS;
> +		if (psr2_su_region_et_valid(intel_dp))
> +			dpcd_val |= DP_PSR_ENABLE_SU_REGION_ET;
>  	} else {
>  		if (intel_dp->psr.link_standby)
>  			dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE; @@ -869,6 +883,9 @@ static void hsw_activate_psr2(struct
> intel_dp *intel_dp)
>  		intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(cpu_transcoder), 0);
>  	}
> 
> +	if (psr2_su_region_et_valid(intel_dp))
> +		val |= LNL_EDP_PSR2_SU_REGION_ET_ENABLE;
> +
>  	/*
>  	 * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is
>  	 * recommending keep this bit unset while PSR2 is enabled.
> @@ -1031,6 +1048,9 @@ static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
>  		return false;
>  	}
> 
> +	if (psr2_su_region_et_valid(intel_dp))
> +		crtc_state->enable_psr2_su_region_et = true;
> +
>  	return crtc_state->enable_psr2_sel_fetch = true;  }
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> index ceefcc70e8f9..bc252f38239e 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> @@ -159,6 +159,7 @@
>  #define   TGL_EDP_PSR2_BLOCK_COUNT_MASK		REG_BIT(28)
>  #define   TGL_EDP_PSR2_BLOCK_COUNT_NUM_2	REG_FIELD_PREP(TGL_EDP_PSR2_BLOCK_COUNT_MASK, 0)
>  #define   TGL_EDP_PSR2_BLOCK_COUNT_NUM_3	REG_FIELD_PREP(TGL_EDP_PSR2_BLOCK_COUNT_MASK, 1)
> +#define   LNL_EDP_PSR2_SU_REGION_ET_ENABLE	REG_BIT(27)
>  #define   EDP_Y_COORDINATE_ENABLE		REG_BIT(25) /* display 10, 11 and 12 */
>  #define   EDP_PSR2_SU_SDP_SCANLINE		REG_BIT(25) /* display 13+ */
>  #define   EDP_MAX_SU_DISABLE_TIME_MASK		REG_GENMASK(24, 20)
> --
> 2.34.1