[PATCH 4/6] drm/i915/adlp+: Add DSC early pixel count scaling WA (Wa_1409098942)

[Nautiyal, Ankit K]

On 1/29/2024 11:25 PM, Imre Deak wrote:
> Add a workaround to fix timing issues on links with DSC enabled -
> presumedly related to the audio functionality.
>
> Bspec requires enabling this workaround if audio is enabled on ADLP,
> however Windows enables it whenever DSC is enabled ADLP onwards; follow
> Windows.
>
> Bspec: 50490, 55424
>
> Signed-off-by: Imre Deak <imre.deak at intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_display.c | 13 +++++++++++++
>   drivers/gpu/drm/i915/i915_reg.h              |  3 +++
>   2 files changed, 16 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index a92e959c8ac7b..0f4cd634d7dce 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -435,6 +435,14 @@ void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state)
>   		return;
>   	}
>   
> +	/* Wa_1409098942: adlp+ */
> +	if (DISPLAY_VER(dev_priv) >= 13 &&
> +	    new_crtc_state->dsc.compression_enable) {
> +		val &= ~TRANSCONF_PIXEL_COUNT_SCALING_MASK;
> +		val |= REG_FIELD_PREP(TRANSCONF_PIXEL_COUNT_SCALING_MASK,
> +				      TRANSCONF_PIXEL_COUNT_SCALING_X4);
> +	}
> +
>   	intel_de_write(dev_priv, TRANSCONF(cpu_transcoder),
>   		       val | TRANSCONF_ENABLE);
>   	intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
> @@ -481,6 +489,11 @@ void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state)
>   	if (!IS_I830(dev_priv))
>   		val &= ~TRANSCONF_ENABLE;
>   
> +	/* Wa_1409098942: adlp+ */

Nit pick: extra space before platform,  (not sure if it matters, tbh).

Patch looks good to me.

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal at intel.com>

> +	if (DISPLAY_VER(dev_priv) >= 13 &&
> +	    old_crtc_state->dsc.compression_enable)
> +		val &= ~TRANSCONF_PIXEL_COUNT_SCALING_MASK;
> +
>   	intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val);
>   
>   	if (DISPLAY_VER(dev_priv) >= 12)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index eecbdecb8ed40..b43d1145fa22f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2588,6 +2588,9 @@
>   #define   TRANSCONF_DITHER_TYPE_ST1		REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 1)
>   #define   TRANSCONF_DITHER_TYPE_ST2		REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 2)
>   #define   TRANSCONF_DITHER_TYPE_TEMP		REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 3)
> +#define   TRANSCONF_PIXEL_COUNT_SCALING_MASK	REG_GENMASK(1, 0)
> +#define   TRANSCONF_PIXEL_COUNT_SCALING_X4	1
> +
>   #define _PIPEASTAT		0x70024
>   #define   PIPE_FIFO_UNDERRUN_STATUS		(1UL << 31)
>   #define   SPRITE1_FLIP_DONE_INT_EN_VLV		(1UL << 30)