[PATCH 5/6] drm/i915/mtl+: Disable DP/DSC SF insertion at EOL WA

[Nautiyal, Ankit K]

LGTM.

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal at intel.com>

On 1/29/2024 11:25 PM, Imre Deak wrote:
> Disable the workaround inserting an SF symbol between the last DSC EOC
> symbol and the subsequent BS symbol. The WA is enabled by default -
> based on the register's reset value - and Bspec requires disabling it
> explicitly. Bspec doesn't provide an actual WA ID for this.
>
> Bspec: 50054, 65448, 68849
>
> Signed-off-by: Imre Deak <imre.deak at intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_display.c | 9 +++++++++
>   drivers/gpu/drm/i915/i915_reg.h              | 1 +
>   2 files changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 0f4cd634d7dce..e0b75aa18ae33 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -428,6 +428,15 @@ void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state)
>   		intel_de_rmw(dev_priv, PIPE_ARB_CTL(pipe),
>   			     0, PIPE_ARB_USE_PROG_SLOTS);
>   
> +	if (DISPLAY_VER(dev_priv) >= 14) {
> +		u32 clear = DP_DSC_INSERT_SF_AT_EOL_WA;
> +		u32 set = 0;
> +
> +		intel_de_rmw(dev_priv,
> +			     hsw_chicken_trans_reg(dev_priv, cpu_transcoder),
> +			     clear, set);
> +	}
> +
>   	val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder));
>   	if (val & TRANSCONF_ENABLE) {
>   		/* we keep both pipes enabled on 830 */
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b43d1145fa22f..9873daa16c6a1 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4620,6 +4620,7 @@
>   #define   DDIE_TRAINING_OVERRIDE_VALUE	REG_BIT(16) /* CHICKEN_TRANS_A only */
>   #define   PSR2_ADD_VERTICAL_LINE_COUNT	REG_BIT(15)
>   #define   PSR2_VSC_ENABLE_PROG_HEADER	REG_BIT(12)
> +#define   DP_DSC_INSERT_SF_AT_EOL_WA	REG_BIT(4)
>   
>   #define DISP_ARB_CTL	_MMIO(0x45000)
>   #define   DISP_FBC_MEMORY_WAKE		REG_BIT(31)