[PATCH v5] drm/i915/display: WA for Re-initialize dispcnlunitt1 xosc clock

Kandpal, Suraj suraj.kandpal at intel.com
Tue Jul 9 11:29:39 UTC 2024



> -----Original Message-----
> From: Golani, Mitulkumar Ajitkumar
> <mitulkumar.ajitkumar.golani at intel.com>
> Sent: Monday, July 8, 2024 2:03 PM
> Cc: intel-gfx at lists.freedesktop.org; Kandpal, Suraj
> <suraj.kandpal at intel.com>; Garg, Nemesa <nemesa.garg at intel.com>;
> Nikula, Jani <jani.nikula at intel.com>
> Subject: [PATCH v5] drm/i915/display: WA for Re-initialize dispcnlunitt1 xosc
> clock
> 
> The dispcnlunit1_cp_xosc_clk should be de-asserted in display off and only
> asserted in display on. As part of this workaround, Display driver shall
> execute set-reset sequence at the end of the initialize sequence to ensure clk
> does not remain active in display OFF.
> 
> HSD: 15013987218
> 
> --v2:
> - Rebase.
> --v3:
> - Correct HSD number in commit message.
> --v4:
> - Reformat commit message.
> - Use intel_de_rmw instead of intel_de_write
> --v5:
> - Build Fixes.
> 

Move the HSD no here other than that LGTM
Reviewed-by: Suraj Kandpal <suraj.kandpal at intel.com>

> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani at intel.com>
> Reviewed-by: Nemesa Garg <nemesa.garg at intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_power.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index e288a1b21d7e..0af1e34ef2a7 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -1704,6 +1704,14 @@ static void icl_display_core_init(struct
> drm_i915_private *dev_priv,
>  	/* Wa_14011503030:xelpd */
>  	if (DISPLAY_VER(dev_priv) == 13)
>  		intel_de_write(dev_priv, XELPD_DISPLAY_ERR_FATAL_MASK,
> ~0);
> +
> +	/* Wa_15013987218 */
> +	if (DISPLAY_VER(dev_priv) == 20) {
> +		intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D,
> +			     0, PCH_GMBUSUNIT_CLOCK_GATE_DISABLE);
> +		intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D,
> +			     PCH_GMBUSUNIT_CLOCK_GATE_DISABLE, 0);
> +	}
>  }
> 
>  static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
> --
> 2.45.2



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