[PATCH v2 4/6] drm/i915/dp: Keep cached LTTPR mode up-to-date

[Nautiyal, Ankit K]

LGTM.

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal at intel.com>

On 7/9/2024 12:30 AM, Imre Deak wrote:
> Nothing depends on the cached LTTPR mode, however for consistency keep
> it up-to-date with the value programmed to the DPCD register.
>
> Reviewed-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak at intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_dp_link_training.c | 8 +++++++-
>   1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index 56b9c5cb1254d..af0b71bdf1fcf 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -114,7 +114,13 @@ intel_dp_set_lttpr_transparent_mode(struct intel_dp *intel_dp, bool enable)
>   	u8 val = enable ? DP_PHY_REPEATER_MODE_TRANSPARENT :
>   			  DP_PHY_REPEATER_MODE_NON_TRANSPARENT;
>   
> -	return drm_dp_dpcd_write(&intel_dp->aux, DP_PHY_REPEATER_MODE, &val, 1) == 1;
> +	if (drm_dp_dpcd_write(&intel_dp->aux, DP_PHY_REPEATER_MODE, &val, 1) != 1)
> +		return false;
> +
> +	intel_dp->lttpr_common_caps[DP_PHY_REPEATER_MODE -
> +				    DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] = val;
> +
> +	return true;
>   }
>   
>   static bool intel_dp_lttpr_transparent_mode_enabled(struct intel_dp *intel_dp)