[PATCH] drm/i915/dp: Clear VSC SDP during post ddi disable routine

[Kandpal, Suraj]

> -----Original Message-----
> From: Kandpal, Suraj <suraj.kandpal at intel.com>
> Sent: Wednesday, July 24, 2024 10:08 PM
> To: intel-gfx at lists.freedesktop.org
> Cc: jani.nikula at linux.intel.com; Nautiyal, Ankit K
> <ankit.k.nautiyal at intel.com>; Kandpal, Suraj <suraj.kandpal at intel.com>
> Subject: [PATCH] drm/i915/dp: Clear VSC SDP during post ddi disable routine
> 
> Clear VSC SDP if intel_dp_set_infoframes is called from post ddi disable
> routine i.e with the variable of enable as false. This is to avoid an
> infoframes.enable mismatch issue which is caused when pipe is connected
> to eDp which has psr then connected to DPMST. In this case eDp's post ddi
> disable routine does not clear infoframes.enable VSC for the given pipe and
> DPMST does not recompute VSC SDP and write infoframes.enable which
> causes a mismatch.
> 
> --v2
> -Make the comment match the code [Jani]
> 
> Signed-off-by: Suraj Kandpal <suraj.kandpal at intel.com>
> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal at intel.com>

Thanks for all reviews pushed to drm-intel-next
Regards,
Suraj Kandpal
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 7 +++++--
>  1 file changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 1e43e32e0519..37cd7165a5b3 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -4369,8 +4369,11 @@ void intel_dp_set_infoframes(struct
> intel_encoder *encoder,
>  	if (!enable && HAS_DSC(dev_priv))
>  		val &= ~VDIP_ENABLE_PPS;
> 
> -	/* When PSR is enabled, this routine doesn't disable VSC DIP */
> -	if (!crtc_state->has_psr)
> +	/*
> +	 * This routine disables VSC DIP if the function is called
> +	 * to disable SDP or if it does not have PSR
> +	 */
> +	if (!enable || !crtc_state->has_psr)
>  		val &= ~VIDEO_DIP_ENABLE_VSC_HSW;
> 
>  	intel_de_write(dev_priv, reg, val);
> --
> 2.43.2