[PATCH v2] drm/i915: Add Wa_14019789679

[Gote, Nitin R]

Hi,

> -----Original Message-----
> From: Jani Nikula <jani.nikula at linux.intel.com>
> Sent: Tuesday, July 30, 2024 1:14 PM
> To: Gote, Nitin R <nitin.r.gote at intel.com>; intel-gfx at lists.freedesktop.org;
> Upadhyay, Tejas <tejas.upadhyay at intel.com>; Roper, Matthew D
> <matthew.d.roper at intel.com>
> Cc: Shyti, Andi <andi.shyti at intel.com>; Wilson, Chris P
> <chris.p.wilson at intel.com>; Gote, Nitin R <nitin.r.gote at intel.com>
> Subject: Re: [PATCH v2] drm/i915: Add Wa_14019789679
> 
> On Tue, 30 Jul 2024, Nitin Gote <nitin.r.gote at intel.com> wrote:
> > Wa_14019789679 implementation for MTL, ARL and DG2.
> >
> > v2: Corrected condition
> >
> > Bspec: 47083
> >
> > Signed-off-by: Nitin Gote <nitin.r.gote at intel.com>
> > ---
> >  drivers/gpu/drm/i915/gt/intel_gpu_commands.h |  1 +
> > drivers/gpu/drm/i915/gt/intel_workarounds.c  | 14 +++++++++++++-
> >  2 files changed, 14 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> > b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> > index 2bd8d98d2110..c143d8133a28 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> > @@ -220,6 +220,7 @@
> >  #define GFX_OP_DESTBUFFER_INFO
> ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
> >  #define GFX_OP_DRAWRECT_INFO
> ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
> >  #define GFX_OP_DRAWRECT_INFO_I965  ((0x7900<<16)|0x2)
> > +#define CMD_3DSTATE_MESH_CONTROL
> > +((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x77<<16)|(0x3))
> >
> >  #define XY_CTRL_SURF_INSTR_SIZE		5
> >  #define MI_FLUSH_DW_SIZE		3
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index 09a287c1aedd..cbc2003886d5 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -974,7 +974,12 @@ int intel_engine_emit_ctx_wa(struct i915_request
> *rq)
> >  	if (ret)
> >  		return ret;
> >
> > -	cs = intel_ring_begin(rq, (wal->count * 2 + 2));
> > +	if ((GRAPHICS_VER_FULL(rq->i915) >= IP_VER(12, 70) &&
> > +			GRAPHICS_VER_FULL(rq->i915) <= IP_VER(12, 74)) ||
> > +IS_DG2(rq->i915))
> 
> Please use checkpatch and get the indentation right.
> 
> BR,
> Jani.

Thank you for review. I will take care indentation in v3 version.

- Nitin

> 
> > +		cs = intel_ring_begin(rq, (wal->count * 2 + 4));
> > +	else
> > +		cs = intel_ring_begin(rq, (wal->count * 2 + 2));
> > +
> >  	if (IS_ERR(cs))
> >  		return PTR_ERR(cs);
> >
> > @@ -1004,6 +1009,13 @@ int intel_engine_emit_ctx_wa(struct
> i915_request *rq)
> >  	}
> >  	*cs++ = MI_NOOP;
> >
> > +	/* Wa_14019789679 */
> > +	if ((GRAPHICS_VER_FULL(rq->i915) >= IP_VER(12, 70) &&
> > +			GRAPHICS_VER_FULL(rq->i915) <= IP_VER(12, 74)) ||
> IS_DG2(rq->i915)) {
> > +		*cs++ = CMD_3DSTATE_MESH_CONTROL;
> > +		*cs++ = MI_NOOP;
> > +	}
> > +
> >  	intel_uncore_forcewake_put__locked(uncore, fw);
> >  	spin_unlock(&uncore->lock);
> >  	intel_gt_mcr_unlock(wal->gt, flags);
> 
> --
> Jani Nikula, Intel