[PATCH 19/65] drm/i915: pass dev_priv explicitly to PIPEDSL

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:25:37PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the PIPEDSL register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi at intel.com>

> 
> Signed-off-by: Jani Nikula <jani.nikula at intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_crt.c    | 6 +++---
>  drivers/gpu/drm/i915/display/intel_hdmi.c   | 3 ++-
>  drivers/gpu/drm/i915/display/intel_vblank.c | 7 ++++---
>  drivers/gpu/drm/i915/i915_reg.h             | 2 +-
>  drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 8 ++++----
>  5 files changed, 14 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
> index d4f16d894eda..835c8b844494 100644
> --- a/drivers/gpu/drm/i915/display/intel_crt.c
> +++ b/drivers/gpu/drm/i915/display/intel_crt.c
> @@ -771,9 +771,9 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
>  		/*
>  		 * Wait for the border to be displayed
>  		 */
> -		while (intel_de_read(dev_priv, PIPEDSL(pipe)) >= vactive)
> +		while (intel_de_read(dev_priv, PIPEDSL(dev_priv, pipe)) >= vactive)
>  			;
> -		while ((dsl = intel_de_read(dev_priv, PIPEDSL(pipe))) <= vsample)
> +		while ((dsl = intel_de_read(dev_priv, PIPEDSL(dev_priv, pipe))) <= vsample)
>  			;
>  		/*
>  		 * Watch ST00 for an entire scanline
> @@ -786,7 +786,7 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
>  			st00 = intel_de_read8(dev_priv, _VGA_MSR_WRITE);
>  			if (st00 & (1 << 4))
>  				detect++;
> -		} while ((intel_de_read(dev_priv, PIPEDSL(pipe)) == dsl));
> +		} while ((intel_de_read(dev_priv, PIPEDSL(dev_priv, pipe)) == dsl));
>  
>  		/* restore vblank if necessary */
>  		if (restore_vblank)
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 06ec9ce7fe1c..7704ead5002d 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -1476,7 +1476,8 @@ static int kbl_repositioning_enc_en_signal(struct intel_connector *connector,
>  	int ret;
>  
>  	for (;;) {
> -		scanline = intel_de_read(dev_priv, PIPEDSL(crtc->pipe));
> +		scanline = intel_de_read(dev_priv,
> +					 PIPEDSL(dev_priv, crtc->pipe));
>  		if (scanline > 100 && scanline < 200)
>  			break;
>  		usleep_range(25, 50);
> diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
> index eb80952b0cfd..e2d20064e68d 100644
> --- a/drivers/gpu/drm/i915/display/intel_vblank.c
> +++ b/drivers/gpu/drm/i915/display/intel_vblank.c
> @@ -247,7 +247,7 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
>  
>  	vtotal = intel_mode_vtotal(mode);
>  
> -	position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & PIPEDSL_LINE_MASK;
> +	position = intel_de_read_fw(dev_priv, PIPEDSL(dev_priv, pipe)) & PIPEDSL_LINE_MASK;
>  
>  	/*
>  	 * On HSW, the DSL reg (0x70000) appears to return 0 if we
> @@ -266,7 +266,8 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
>  
>  		for (i = 0; i < 100; i++) {
>  			udelay(1);
> -			temp = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & PIPEDSL_LINE_MASK;
> +			temp = intel_de_read_fw(dev_priv,
> +						PIPEDSL(dev_priv, pipe)) & PIPEDSL_LINE_MASK;
>  			if (temp != position) {
>  				position = temp;
>  				break;
> @@ -473,7 +474,7 @@ int intel_get_crtc_scanline(struct intel_crtc *crtc)
>  static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv,
>  				    enum pipe pipe)
>  {
> -	i915_reg_t reg = PIPEDSL(pipe);
> +	i915_reg_t reg = PIPEDSL(dev_priv, pipe);
>  	u32 line1, line2;
>  
>  	line1 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 72f5140cf109..fbd004bd1992 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1877,7 +1877,7 @@
>  #define PIPESTAT_INT_STATUS_MASK		0x0000ffff
>  
>  #define TRANSCONF(dev_priv, trans)	_MMIO_PIPE2(dev_priv, (trans), _TRANSACONF)
> -#define PIPEDSL(pipe)		_MMIO_PIPE2(dev_priv, pipe, _PIPEADSL)
> +#define PIPEDSL(dev_priv, pipe)		_MMIO_PIPE2(dev_priv, pipe, _PIPEADSL)
>  #define PIPEFRAME(pipe)		_MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEHIGH)
>  #define PIPEFRAMEPIXEL(pipe)	_MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEPIXEL)
>  #define PIPESTAT(pipe)		_MMIO_PIPE2(dev_priv, pipe, _PIPEASTAT)
> diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> index 436d4a2eccd7..6a37f790c753 100644
> --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> @@ -126,10 +126,10 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(_MMIO(0x650b4));
>  	MMIO_D(_MMIO(0xc4040));
>  	MMIO_D(DERRMR);
> -	MMIO_D(PIPEDSL(PIPE_A));
> -	MMIO_D(PIPEDSL(PIPE_B));
> -	MMIO_D(PIPEDSL(PIPE_C));
> -	MMIO_D(PIPEDSL(_PIPE_EDP));
> +	MMIO_D(PIPEDSL(dev_priv, PIPE_A));
> +	MMIO_D(PIPEDSL(dev_priv, PIPE_B));
> +	MMIO_D(PIPEDSL(dev_priv, PIPE_C));
> +	MMIO_D(PIPEDSL(dev_priv, _PIPE_EDP));
>  	MMIO_D(TRANSCONF(dev_priv, TRANSCODER_A));
>  	MMIO_D(TRANSCONF(dev_priv, TRANSCODER_B));
>  	MMIO_D(TRANSCONF(dev_priv, TRANSCODER_C));
> -- 
> 2.39.2
>