[PATCH 22/65] drm/i915: pass dev_priv explicitly to PIPESTAT

[Rodrigo Vivi]

On Tue, Jun 04, 2024 at 06:25:40PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the PIPESTAT register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi at intel.com>

> 
> Signed-off-by: Jani Nikula <jani.nikula at intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_irq.c   | 9 +++++----
>  drivers/gpu/drm/i915/display/intel_fifo_underrun.c | 4 ++--
>  drivers/gpu/drm/i915/i915_reg.h                    | 2 +-
>  drivers/gpu/drm/i915/intel_gvt_mmio_table.c        | 8 ++++----
>  4 files changed, 12 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
> index be5b48861baf..76bba95410e7 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
> @@ -224,7 +224,7 @@ u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
>  void i915_enable_pipestat(struct drm_i915_private *dev_priv,
>  			  enum pipe pipe, u32 status_mask)
>  {
> -	i915_reg_t reg = PIPESTAT(pipe);
> +	i915_reg_t reg = PIPESTAT(dev_priv, pipe);
>  	u32 enable_mask;
>  
>  	drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK,
> @@ -247,7 +247,7 @@ void i915_enable_pipestat(struct drm_i915_private *dev_priv,
>  void i915_disable_pipestat(struct drm_i915_private *dev_priv,
>  			   enum pipe pipe, u32 status_mask)
>  {
> -	i915_reg_t reg = PIPESTAT(pipe);
> +	i915_reg_t reg = PIPESTAT(dev_priv, pipe);
>  	u32 enable_mask;
>  
>  	drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK,
> @@ -400,7 +400,8 @@ void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv)
>  	enum pipe pipe;
>  
>  	for_each_pipe(dev_priv, pipe) {
> -		intel_uncore_write(&dev_priv->uncore, PIPESTAT(pipe),
> +		intel_uncore_write(&dev_priv->uncore,
> +				   PIPESTAT(dev_priv, pipe),
>  				   PIPESTAT_INT_STATUS_MASK |
>  				   PIPE_FIFO_UNDERRUN_STATUS);
>  
> @@ -453,7 +454,7 @@ void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv,
>  		if (!status_mask)
>  			continue;
>  
> -		reg = PIPESTAT(pipe);
> +		reg = PIPESTAT(dev_priv, pipe);
>  		pipe_stats[pipe] = intel_uncore_read(&dev_priv->uncore, reg) & status_mask;
>  		enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> index 09a7fa6c0c37..401726f466c0 100644
> --- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> +++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> @@ -94,7 +94,7 @@ static bool cpt_can_enable_serr_int(struct drm_device *dev)
>  static void i9xx_check_fifo_underruns(struct intel_crtc *crtc)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> -	i915_reg_t reg = PIPESTAT(crtc->pipe);
> +	i915_reg_t reg = PIPESTAT(dev_priv, crtc->pipe);
>  	u32 enable_mask;
>  
>  	lockdep_assert_held(&dev_priv->irq_lock);
> @@ -115,7 +115,7 @@ static void i9xx_set_fifo_underrun_reporting(struct drm_device *dev,
>  					     bool enable, bool old)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(dev);
> -	i915_reg_t reg = PIPESTAT(pipe);
> +	i915_reg_t reg = PIPESTAT(dev_priv, pipe);
>  
>  	lockdep_assert_held(&dev_priv->irq_lock);
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a6dff480bd0b..0aaceedf77dc 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1880,7 +1880,7 @@
>  #define PIPEDSL(dev_priv, pipe)		_MMIO_PIPE2(dev_priv, pipe, _PIPEADSL)
>  #define PIPEFRAME(dev_priv, pipe)		_MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEHIGH)
>  #define PIPEFRAMEPIXEL(dev_priv, pipe)	_MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEPIXEL)
> -#define PIPESTAT(pipe)		_MMIO_PIPE2(dev_priv, pipe, _PIPEASTAT)
> +#define PIPESTAT(dev_priv, pipe)		_MMIO_PIPE2(dev_priv, pipe, _PIPEASTAT)
>  
>  #define _PIPE_ARB_CTL_A			0x70028 /* icl+ */
>  #define PIPE_ARB_CTL(pipe)		_MMIO_PIPE2(dev_priv, pipe, _PIPE_ARB_CTL_A)
> diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> index 6a37f790c753..00ee588fab39 100644
> --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> @@ -134,10 +134,10 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(TRANSCONF(dev_priv, TRANSCODER_B));
>  	MMIO_D(TRANSCONF(dev_priv, TRANSCODER_C));
>  	MMIO_D(TRANSCONF(dev_priv, TRANSCODER_EDP));
> -	MMIO_D(PIPESTAT(PIPE_A));
> -	MMIO_D(PIPESTAT(PIPE_B));
> -	MMIO_D(PIPESTAT(PIPE_C));
> -	MMIO_D(PIPESTAT(_PIPE_EDP));
> +	MMIO_D(PIPESTAT(dev_priv, PIPE_A));
> +	MMIO_D(PIPESTAT(dev_priv, PIPE_B));
> +	MMIO_D(PIPESTAT(dev_priv, PIPE_C));
> +	MMIO_D(PIPESTAT(dev_priv, _PIPE_EDP));
>  	MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A));
>  	MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B));
>  	MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C));
> -- 
> 2.39.2
>