[PATCH] drm/i915: Skip programming FIA link enable bits for MTL+

[Gustavo Sousa]

Quoting Imre Deak (2024-06-26 13:24:24-03:00)
>On Tue, Jun 25, 2024 at 05:26:52PM -0300, Gustavo Sousa wrote:
>> Starting with Xe_LPDP, support for Type-C connections is provided by
>> PICA and programming PORT_TX_DFLEXDPMLE1(*) registers is not applicable
>> anymore. Those registers don't even exist in recent display IPs. As
>> such, skip programming them.
>> 
>> Bspec: 65750, 65448
>> Signed-off-by: Gustavo Sousa <gustavo.sousa at intel.com>
>
>MTL still has a FIA mux and the DP-alt pin configuration is read out

Yep. Maybe I could rephrase the commit message like below?

  Starting with Xe_LPDP, although FIA is still used to readout Type-C
  pin assignment, part of Type-C support is moved to PICA and
  programming PORT_TX_DFLEXDPMLE1(*) registers is not applicable
  anymore.

>from that, but programming DPMLE1 accordingly doesn't seem to be
>required indeed (the register still exists but programming it doesn't
>make a difference based on my test):

Well, yes, one of the base offsets (0x16f8c0) does exist on MTL, but it
maps to a completely different register (according to the register
database).

>
>Reviewed-by: Imre Deak <imre.deak at intel.com>

Thanks!

Gustavo Sousa

>
>> ---
>>  drivers/gpu/drm/i915/display/intel_tc.c | 3 +++
>>  1 file changed, 3 insertions(+)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
>> index 9887967b2ca5..6f2ee7dbc43b 100644
>> --- a/drivers/gpu/drm/i915/display/intel_tc.c
>> +++ b/drivers/gpu/drm/i915/display/intel_tc.c
>> @@ -393,6 +393,9 @@ void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
>>          bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
>>          u32 val;
>>  
>> +        if (DISPLAY_VER(i915) >= 14)
>> +                return;
>> +
>>          drm_WARN_ON(&i915->drm,
>>                      lane_reversal && tc->mode != TC_PORT_LEGACY);
>>  
>> -- 
>> 2.45.2
>>