[PATCH 1/5] drm/i915/display: Add support for SNPS PHY HDMI PLL algorithm for DG2
kernel test robot
lkp at intel.com
Wed Jun 26 18:46:57 UTC 2024
Hi Ankit,
kernel test robot noticed the following build errors:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on drm-intel/for-linux-next-fixes drm-tip/drm-tip drm-xe/drm-xe-next linus/master v6.10-rc5 next-20240625]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Ankit-Nautiyal/drm-i915-display-Add-support-for-SNPS-PHY-HDMI-PLL-algorithm-for-DG2/20240626-131209
base: git://anongit.freedesktop.org/drm-intel for-linux-next
patch link: https://lore.kernel.org/r/20240626050056.3996349-2-ankit.k.nautiyal%40intel.com
patch subject: [PATCH 1/5] drm/i915/display: Add support for SNPS PHY HDMI PLL algorithm for DG2
config: i386-randconfig-011-20240626 (https://download.01.org/0day-ci/archive/20240627/202406270253.GoXTAfRN-lkp@intel.com/config)
compiler: clang version 18.1.5 (https://github.com/llvm/llvm-project 617a15a9eac96088ae5e9134248d8236e34b91b1)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240627/202406270253.GoXTAfRN-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp at intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202406270253.GoXTAfRN-lkp@intel.com/
All errors (new ones prefixed by >>):
>> drivers/gpu/drm/i915/display/intel_pll_algorithm.c:153:14: error: variable 'a' is used uninitialized whenever 'for' loop exits because its condition is false [-Werror,-Wsometimes-uninitialized]
153 | for (j = 0; j < 8; j += 2) {
| ^~~~~
drivers/gpu/drm/i915/display/intel_pll_algorithm.c:161:67: note: uninitialized use occurs here
161 | get_ana_cp_int_prop(vco_clk, refclk_postscalar, mpll_ana_v2i, c, a,
| ^
drivers/gpu/drm/i915/display/intel_pll_algorithm.c:153:14: note: remove the condition if it is always true
153 | for (j = 0; j < 8; j += 2) {
| ^~~~~
drivers/gpu/drm/i915/display/intel_pll_algorithm.c:124:10: note: initialize the variable 'a' to silence this warning
124 | int c, a, j;
| ^
| = 0
>> drivers/gpu/drm/i915/display/intel_pll_algorithm.c:153:14: error: variable 'ana_freq_vco' is used uninitialized whenever 'for' loop exits because its condition is false [-Werror,-Wsometimes-uninitialized]
153 | for (j = 0; j < 8; j += 2) {
| ^~~~~
drivers/gpu/drm/i915/display/intel_pll_algorithm.c:179:29: note: uninitialized use occurs here
179 | pll_params->ana_freq_vco = ana_freq_vco;
| ^~~~~~~~~~~~
drivers/gpu/drm/i915/display/intel_pll_algorithm.c:153:14: note: remove the condition if it is always true
153 | for (j = 0; j < 8; j += 2) {
| ^~~~~
drivers/gpu/drm/i915/display/intel_pll_algorithm.c:123:18: note: initialize the variable 'ana_freq_vco' to silence this warning
123 | int ana_freq_vco;
| ^
| = 0
2 errors generated.
vim +153 drivers/gpu/drm/i915/display/intel_pll_algorithm.c
92
93 static int _intel_phy_compute_hdmi_tmds_pll(u64 pixel_clock, u32 refclk,
94 u32 ref_range,
95 u32 ana_cp_int_gs,
96 u32 ana_cp_prop_gs,
97 const u64 curve_freq_hz[2][8],
98 const u64 curve_0[2][8],
99 const u64 curve_1[2][8],
100 const u64 curve_2[2][8],
101 u32 prescaler_divider,
102 struct pll_output_params *pll_params)
103 {
104 /*datarate 10khz */
105 u64 datarate = pixel_clock * 10000;
106 u32 ssc_up_spread = 1;
107 u32 mpll_div5_en = 1;
108 u32 hdmi_div = 1;
109 u32 ana_cp_int;
110 u32 ana_cp_prop;
111 u32 refclk_postscalar = refclk >> prescaler_divider;
112 u32 tx_clk_div;
113 u64 vco_clk;
114 u32 vco_div_refclk_integer;
115 u32 vco_div_refclk_fracn;
116 u32 fracn_quot;
117 u32 fracn_rem;
118 u32 fracn_den;
119 u32 fracn_en;
120 u32 pmix_en;
121 u32 multiplier;
122 int mpll_ana_v2i;
123 int ana_freq_vco;
124 int c, a, j;
125
126 if (pixel_clock < 25175 || pixel_clock > 600000)
127 return -EINVAL;
128
129 /* Select appropriate v2i point */
130 if (datarate <= INTEL_SNPS_PHY_HDMI_9999MHZ) {
131 mpll_ana_v2i = 2;
132 tx_clk_div = ilog2(INTEL_SNPS_PHY_HDMI_9999MHZ / datarate);
133 } else {
134 mpll_ana_v2i = 3;
135 tx_clk_div = ilog2(INTEL_SNPS_PHY_HDMI_16GHZ / datarate);
136 }
137 vco_clk = (datarate << tx_clk_div) >> 1;
138
139 /* Highly accurate division, calculate fraction to 32 bits of precision */
140 vco_div_refclk_integer = vco_clk / refclk_postscalar;
141 vco_div_refclk_fracn = ((vco_clk % refclk_postscalar) << 32) / refclk_postscalar;
142 fracn_quot = vco_div_refclk_fracn >> 16;
143 fracn_rem = vco_div_refclk_fracn & 0xffff;
144 fracn_rem = fracn_rem - (fracn_rem >> 15);
145 fracn_den = 0xffff;
146 fracn_en = (fracn_quot != 0 || fracn_rem != 0) ? 1 : 0;
147 pmix_en = fracn_en;
148 multiplier = (vco_div_refclk_integer - 16) * 2;
149 /* Curve selection for ana_cp_* calculations. One curve hardcoded per v2i range */
150 c = mpll_ana_v2i - 2;
151
152 /* Find the right segment of the table */
> 153 for (j = 0; j < 8; j += 2) {
154 if (vco_clk <= curve_freq_hz[c][j + 1]) {
155 a = j;
156 ana_freq_vco = 3 - (a >> 1);
157 break;
158 }
159 }
160
161 get_ana_cp_int_prop(vco_clk, refclk_postscalar, mpll_ana_v2i, c, a,
162 curve_freq_hz, curve_0, curve_1, curve_2,
163 &ana_cp_int, &ana_cp_prop);
164
165 pll_params->ssc_up_spread = ssc_up_spread;
166 pll_params->mpll_div5_en = mpll_div5_en;
167 pll_params->hdmi_div = hdmi_div;
168 pll_params->ana_cp_int = ana_cp_int;
169 pll_params->refclk_postscalar = refclk_postscalar;
170 pll_params->tx_clk_div = tx_clk_div;
171 pll_params->fracn_quot = fracn_quot;
172 pll_params->fracn_rem = fracn_rem;
173 pll_params->fracn_den = fracn_den;
174 pll_params->fracn_en = fracn_en;
175 pll_params->pmix_en = pmix_en;
176 pll_params->multiplier = multiplier;
177 pll_params->ana_cp_prop = ana_cp_prop;
178 pll_params->mpll_ana_v2i = mpll_ana_v2i;
179 pll_params->ana_freq_vco = ana_freq_vco;
180
181 return 0;
182 }
183
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