[PATCH 2/8] drm/i915/cdclk: Add and use xe2lpd_mdclk_source_sel()

[Gustavo Sousa]

Quoting Matt Roper (2024-03-04 18:58:34-03:00)
>On Mon, Mar 04, 2024 at 03:30:21PM -0300, Gustavo Sousa wrote:
>> There will be future changes that rely on the source of the MDCLK. Let's
>> have xe2lpd_mdclk_source_sel() as the function responsible for reporting
>> that information.
>> 
>> Bspec: 69090
>> Signed-off-by: Gustavo Sousa <gustavo.sousa at intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_cdclk.c | 17 ++++++++++++++++-
>>  drivers/gpu/drm/i915/i915_reg.h            |  4 +++-
>>  2 files changed, 19 insertions(+), 2 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
>> index 407bd541eb46..bf84bf27213f 100644
>> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
>> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
>> @@ -1876,6 +1876,21 @@ static bool cdclk_pll_is_unknown(unsigned int vco)
>>          return vco == ~0;
>>  }
>>  
>> +static u32 xe2lpd_mdclk_source_sel(struct drm_i915_private *i915)
>> +{
>> +        if (DISPLAY_VER(i915) >= 20)
>> +                return MDCLK_SOURCE_SEL_CDCLK_PLL;
>> +
>> +        /*
>> +         * Earlier display IPs do not provide means of selecting the
>> +         * MDCLK source, but MDCLK_SOURCE_SEL_CD2XCLK is a nice default,
>> +         * since it reflects the source used for those and allows
>> +         * xe2lpd_mdclk_source_sel() to be used in logic that depends on
>> +         * it.
>> +         */
>> +        return MDCLK_SOURCE_SEL_CD2XCLK;
>
>At the moment this function only gets called on Xe2 and beyond where the
>register field exists; if that's going to change soon, then wouldn't it
>be more natural to just use an early exit to highlight that there's
>nothing we need to OR into the CDCLK_CTL for earlier platforms?  
>
>    /* Not configurable for older platforms; they always use CD2XCLK */
>    if (DISPLAY_VER(i915) < 20)
>            return 0;
>
>Functionally it's the same, but it feels more intuitive to me.
>
>If we aren't expecting to call this from common codepaths that aren't
>already protected by a display version check, then we could make this a
>drm_WARN_ON() to assert that we haven't deviated from expected behavior.

Well, the intention here was for this function to serve 2 purposes: (i)
to give the value of the "MDCLK Source Select" field of CDCLK_CTL and
also (ii) tell which was the source of the MDCLK for displays pre and
post (including) Xe2LPD, because we will need that information in
"drm/i915: Add mdclk_cdclk_ratio to intel_dbuf_state".

I was hoping to do that instead of creating a new enum, but maybe it
will just cause confusion?

Should we have one function to tell us the source and another for
giving the value of the register field?

--
Gustavo Sousa

>
>
>Matt
>
>> +}
>> +
>>  static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i915,
>>                                                      const struct intel_cdclk_config *old_cdclk_config,
>>                                                      const struct intel_cdclk_config *new_cdclk_config,
>> @@ -1980,7 +1995,7 @@ static u32 bxt_cdclk_ctl(struct drm_i915_private *i915,
>>                  val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
>>  
>>          if (DISPLAY_VER(i915) >= 20)
>> -                val |= MDCLK_SOURCE_SEL_CDCLK_PLL;
>> +                val |= xe2lpd_mdclk_source_sel(i915);
>>          else
>>                  val |= skl_cdclk_decimal(cdclk);
>>  
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index e00557e1a57f..eb953ed1f113 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -5900,7 +5900,9 @@ enum skl_power_gate {
>>  #define  CDCLK_FREQ_540                REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 1)
>>  #define  CDCLK_FREQ_337_308                REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 2)
>>  #define  CDCLK_FREQ_675_617                REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 3)
>> -#define  MDCLK_SOURCE_SEL_CDCLK_PLL        REG_BIT(25)
>> +#define  MDCLK_SOURCE_SEL_MASK                REG_GENMASK(25, 25)
>> +#define  MDCLK_SOURCE_SEL_CD2XCLK        REG_FIELD_PREP(MDCLK_SOURCE_SEL_MASK, 0)
>> +#define  MDCLK_SOURCE_SEL_CDCLK_PLL        REG_FIELD_PREP(MDCLK_SOURCE_SEL_MASK, 1)
>>  #define  BXT_CDCLK_CD2X_DIV_SEL_MASK        REG_GENMASK(23, 22)
>>  #define  BXT_CDCLK_CD2X_DIV_SEL_1        REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 0)
>>  #define  BXT_CDCLK_CD2X_DIV_SEL_1_5        REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 1)
>> -- 
>> 2.44.0
>> 
>
>-- 
>Matt Roper
>Graphics Software Engineer
>Linux GPU Platform Enablement
>Intel Corporation