[PATCH 1/3] drm/i915/vrr: Generate VRR "safe window" for DSB

[Manna, Animesh]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces at lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Wednesday, March 6, 2024 9:38 AM
> To: intel-gfx at lists.freedesktop.org
> Cc: stable at vger.kernel.org
> Subject: [PATCH 1/3] drm/i915/vrr: Generate VRR "safe window" for DSB
> 
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> Looks like TRANS_CHICKEN bit 31 means something totally different
> depending on the platform:
> TGL: generate VRR "safe window" for DSB
> ADL/DG2: make TRANS_SET_CONTEXT_LATENCY effective with VRR
> 
> So far we've only set this on ADL/DG2, but when using DSB+VRR we also
> need to set it on TGL.
> 
> And a quick test on MTL says it doesn't need this bit for either of those
> purposes, even though it's still documented as valid in bspec.
> 
> Cc: stable at vger.kernel.org
> Fixes: 34d8311f4a1c ("drm/i915/dsb: Re-instate DSB for LUT updates")
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9927
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

LGTM.
Reviewed-by: Animesh Manna <animesh.manna at intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_vrr.c | 7 ++++---
>  drivers/gpu/drm/i915/i915_reg.h          | 2 +-
>  2 files changed, 5 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
> b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 5d905f932cb4..eb5bd0743902 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -187,10 +187,11 @@ void intel_vrr_set_transcoder_timings(const struct
> intel_crtc_state *crtc_state)
>  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> 
>  	/*
> -	 * TRANS_SET_CONTEXT_LATENCY with VRR enabled
> -	 * requires this chicken bit on ADL/DG2.
> +	 * This bit seems to have two meanings depending on the platform:
> +	 * TGL: generate VRR "safe window" for DSB vblank waits
> +	 * ADL/DG2: make TRANS_SET_CONTEXT_LATENCY effective with VRR
>  	 */
> -	if (DISPLAY_VER(dev_priv) == 13)
> +	if (IS_DISPLAY_VER(dev_priv, 12, 13))
>  		intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder),
>  			     0, PIPE_VBLANK_WITH_DELAY);
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h index e00557e1a57f..3b2e49ce29ba
> 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4599,7 +4599,7 @@
>  #define MTL_CHICKEN_TRANS(trans)	_MMIO_TRANS((trans), \
>  						    _MTL_CHICKEN_TRANS_A,
> \
>  						    _MTL_CHICKEN_TRANS_B)
> -#define   PIPE_VBLANK_WITH_DELAY	REG_BIT(31) /* ADL/DG2 */
> +#define   PIPE_VBLANK_WITH_DELAY	REG_BIT(31) /* tgl+ */
>  #define   SKL_UNMASK_VBL_TO_PIPE_IN_SRD	REG_BIT(30) /* skl+ */
>  #define   HSW_FRAME_START_DELAY_MASK	REG_GENMASK(28, 27)
>  #define   HSW_FRAME_START_DELAY(x)
> 	REG_FIELD_PREP(HSW_FRAME_START_DELAY_MASK, x)
> --
> 2.43.0