[PATCH] drm/i915: Drop WA 16015675438

Rodrigo Vivi rodrigo.vivi at intel.com
Mon Mar 11 14:54:57 UTC 2024


On Wed, Mar 06, 2024 at 06:43:39AM -0800, Lucas De Marchi wrote:
> With dynamic load-balancing disabled on the compute side, there's no
> reason left to enable WA 16015675438. Drop it from both PVC and DG2.
> Note that this can be done because now the driver always set a fixed
> partition of EUs during initialization via the ccs_mode configuration.
> 
> The flag to GuC is still needed because of 18020744125, so update
> the comment accordingly.
> 
> Cc: Rodrigo Vivi <rodrigo.vivi at intel.com>
> Acked-by: Mateusz Jablonski <mateusz.jablonski at intel.com>
> Acked-by: Michal Mrozek <michal.mrozek at intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi at intel.com>

> ---
> 
> This is the i915 counter part. The xe version of this patch
> (https://lore.kernel.org/intel-xe/20240304233103.1687412-1-lucas.demarchi@intel.com/)
> was already merged in drm-xe-next. I'm keeping the acked-by as it also
> applies the same logic in i915.
> 
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 +-----
>  drivers/gpu/drm/i915/gt/uc/intel_guc.c      | 2 +-
>  2 files changed, 2 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index d67d44611c28..7f812409c30a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -2928,14 +2928,10 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
>  		wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE);
>  	}
>  
> -	if (IS_PONTEVECCHIO(i915) || IS_DG2(i915)) {
> +	if (IS_PONTEVECCHIO(i915) || IS_DG2(i915))
>  		/* Wa_14015227452:dg2,pvc */
>  		wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE);
>  
> -		/* Wa_16015675438:dg2,pvc */
> -		wa_masked_en(wal, FF_SLICE_CS_CHICKEN2, GEN12_PERF_FIX_BALANCING_CFE_DISABLE);
> -	}
> -
>  	if (IS_DG2(i915)) {
>  		/*
>  		 * Wa_16011620976:dg2_g11
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> index d2b7425bbdcc..c6603793af89 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> @@ -315,7 +315,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
>  	if (IS_DG2_G11(gt->i915))
>  		flags |= GUC_WA_CONTEXT_ISOLATION;
>  
> -	/* Wa_16015675438 */
> +	/* Wa_18020744125 */
>  	if (!RCS_MASK(gt))
>  		flags |= GUC_WA_RCS_REGS_IN_CCS_REGS_LIST;
>  
> -- 
> 2.43.0
> 


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