[PATCH] drm/i915/mtl: Add Wa_14020495402

[Matt Roper]

On Mon, Mar 18, 2024 at 12:35:58PM -0700, Radhakrishna Sripada wrote:
> Disable clockgating for TDL SVHS fub.
> 
> Bspec: 46045
> Cc: Matt Roper <matthew.d.roper at intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada at intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_gt_regs.h     | 1 +
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++
>  2 files changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 50962cfd1353..860765cd2ad2 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -1215,6 +1215,7 @@
>  #define   GEN12_DISABLE_EARLY_READ		REG_BIT(14)
>  #define   GEN12_ENABLE_LARGE_GRF_MODE		REG_BIT(12)
>  #define   GEN12_PUSH_CONST_DEREF_HOLD_DIS	REG_BIT(8)
> +#define   MTL_DISABLE_TDL_SVHS_GATING		REG_BIT(1)
>  #define   GEN12_DISABLE_DOP_GATING              REG_BIT(0)
>  
>  #define RT_CTRL					MCR_REG(0xe530)
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index b079cbbc1897..8a82aa93a08d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -828,6 +828,9 @@ static void xelpg_ctx_workarounds_init(struct intel_engine_cs *engine,
>  
>  	/* Wa_14019877138 */
>  	wa_mcr_masked_en(wal, XEHP_PSS_CHICKEN, FD_END_COLLECT);
> +
> +	/* Wa_14020495402 */
> +	wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, MTL_DISABLE_TDL_SVHS_GATING);

I don't see this register in the LRC.  I think this might be in the
wrong function?

Also, this patch should use an xelpg prefix, not MTL, since this is a
workaround for the graphics IP (on any platform it shows up in), not for
MTL.


Matt

>  }
>  
>  static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine,
> -- 
> 2.34.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation