[PATCH v20 8/9] drm/i915/display: Compute vrr_vsync params
Nautiyal, Ankit K
ankit.k.nautiyal at intel.com
Thu Mar 21 04:08:39 UTC 2024
LGTM.
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal at intel.com>
On 3/20/2024 10:30 AM, Mitul Golani wrote:
> Compute vrr_vsync_start/end, which sets the position
> for hardware to send the Vsync at a fixed position
> relative to the end of the Vblank.
>
> --v2:
> - Updated VSYNC_START/END macros to VRR_VSYNC_START/END. (Ankit)
> - Updated bit fields of VRR_VSYNC_START/END. (Ankit)
>
> --v3:
> - Add PIPE_CONF_CHECK_I(vrr.vsync_start/end).
> - Read/write vrr_vsync params only when we intend to send
> adaptive_sync sdp.
>
> --v4:
> - Use VRR_SYNC_START/END macros correctly.
>
> --v5:
> - Send AS SDP only when VRR is enabled.
>
> --v6:
> - Add TRANS_VRR_VSYNC befor enabling VRR as per bspec. (Ankit)
>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani at intel.com>
> Reviewed-by: Arun R Murthy <arun.r.murthy at intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 2 ++
> .../drm/i915/display/intel_display_types.h | 1 +
> drivers/gpu/drm/i915/display/intel_vrr.c | 33 +++++++++++++++++--
> drivers/gpu/drm/i915/i915_reg.h | 7 ++++
> 4 files changed, 41 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index eb8f36b38c41..9e5924e21eee 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5356,6 +5356,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> PIPE_CONF_CHECK_I(vrr.flipline);
> PIPE_CONF_CHECK_I(vrr.pipeline_full);
> PIPE_CONF_CHECK_I(vrr.guardband);
> + PIPE_CONF_CHECK_I(vrr.vsync_start);
> + PIPE_CONF_CHECK_I(vrr.vsync_end);
> }
>
> #undef PIPE_CONF_CHECK_X
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 36fcded7564a..95da3cf27188 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1431,6 +1431,7 @@ struct intel_crtc_state {
> bool enable, in_range;
> u8 pipeline_full;
> u16 flipline, vmin, vmax, guardband;
> + u32 vsync_end, vsync_start;
> } vrr;
>
> /* Stream Splitter for eDP MSO */
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index eb5bd0743902..856378f8b90e 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -9,6 +9,7 @@
> #include "intel_de.h"
> #include "intel_display_types.h"
> #include "intel_vrr.h"
> +#include "intel_dp.h"
>
> bool intel_vrr_is_capable(struct intel_connector *connector)
> {
> @@ -113,6 +114,7 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
> struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> struct intel_connector *connector =
> to_intel_connector(conn_state->connector);
> + struct intel_dp *intel_dp = intel_attached_dp(connector);
> struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> const struct drm_display_info *info = &connector->base.display_info;
> int vmin, vmax;
> @@ -165,6 +167,14 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
> if (crtc_state->uapi.vrr_enabled) {
> crtc_state->vrr.enable = true;
> crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
> + if (intel_dp_as_sdp_supported(intel_dp)) {
> + crtc_state->vrr.vsync_start =
> + (crtc_state->hw.adjusted_mode.crtc_vtotal -
> + crtc_state->hw.adjusted_mode.vsync_start);
> + crtc_state->vrr.vsync_end =
> + (crtc_state->hw.adjusted_mode.crtc_vtotal -
> + crtc_state->hw.adjusted_mode.vsync_end);
> + }
> }
> }
>
> @@ -240,6 +250,12 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
> return;
>
> intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), TRANS_PUSH_EN);
> +
> + if (HAS_AS_SDP(dev_priv))
> + intel_de_write(dev_priv, TRANS_VRR_VSYNC(cpu_transcoder),
> + VRR_VSYNC_END(crtc_state->vrr.vsync_end) |
> + VRR_VSYNC_START(crtc_state->vrr.vsync_start));
> +
> intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder),
> VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state));
> }
> @@ -258,13 +274,16 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
> intel_de_wait_for_clear(dev_priv, TRANS_VRR_STATUS(cpu_transcoder),
> VRR_STATUS_VRR_EN_LIVE, 1000);
> intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), 0);
> +
> + if (HAS_AS_SDP(dev_priv))
> + intel_de_write(dev_priv, TRANS_VRR_VSYNC(cpu_transcoder), 0);
> }
>
> void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> - u32 trans_vrr_ctl;
> + u32 trans_vrr_ctl, trans_vrr_vsync;
>
> trans_vrr_ctl = intel_de_read(dev_priv, TRANS_VRR_CTL(cpu_transcoder));
>
> @@ -284,6 +303,16 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
> crtc_state->vrr.vmin = intel_de_read(dev_priv, TRANS_VRR_VMIN(cpu_transcoder)) + 1;
> }
>
> - if (crtc_state->vrr.enable)
> + if (crtc_state->vrr.enable) {
> crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
> +
> + if (HAS_AS_SDP(dev_priv)) {
> + trans_vrr_vsync =
> + intel_de_read(dev_priv, TRANS_VRR_VSYNC(cpu_transcoder));
> + crtc_state->vrr.vsync_start =
> + REG_FIELD_GET(VRR_VSYNC_START_MASK, trans_vrr_vsync);
> + crtc_state->vrr.vsync_end =
> + REG_FIELD_GET(VRR_VSYNC_END_MASK, trans_vrr_vsync);
> + }
> + }
> }
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3ff6a38826cb..2ede6982175c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2095,6 +2095,13 @@
> #define TRANS_PUSH_EN REG_BIT(31)
> #define TRANS_PUSH_SEND REG_BIT(30)
>
> +#define _TRANS_VRR_VSYNC_A 0x60078
> +#define TRANS_VRR_VSYNC(trans) _MMIO_TRANS2(trans, _TRANS_VRR_VSYNC_A)
> +#define VRR_VSYNC_END_MASK REG_GENMASK(28, 16)
> +#define VRR_VSYNC_END(vsync_end) REG_FIELD_PREP(VRR_VSYNC_END_MASK, (vsync_end))
> +#define VRR_VSYNC_START_MASK REG_GENMASK(12, 0)
> +#define VRR_VSYNC_START(vsync_start) REG_FIELD_PREP(VRR_VSYNC_START_MASK, (vsync_start))
> +
> /* VGA port control */
> #define ADPA _MMIO(0x61100)
> #define PCH_ADPA _MMIO(0xe1100)
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