[PATCH v4 1/5] drm/i915/psr: Add missing ALPM AUX-Less register definitions

[Murthy, Arun R]

> -----Original Message-----
> From: Hogander, Jouni <jouni.hogander at intel.com>
> Sent: Friday, March 15, 2024 1:32 PM
> To: intel-gfx at lists.freedesktop.org
> Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>; Manna, Animesh
> <animesh.manna at intel.com>; Murthy, Arun R <arun.r.murthy at intel.com>;
> Hogander, Jouni <jouni.hogander at intel.com>
> Subject: [PATCH v4 1/5] drm/i915/psr: Add missing ALPM AUX-Less register
> definitions
> 
> Couple of ALPM AUX-Less related fields are missing from ALPM register
> definitions. Add these and remove some duplicate definitions.
> 
> Bspec: 70294
> 
> V2: add Bspec reference
> 
> Signed-off-by: Jouni Högander <jouni.hogander at intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy at intel.com>

Thanks and Regards,
Arun R Murthy
-------------------
> ---
>  drivers/gpu/drm/i915/display/intel_psr_regs.h | 12 ++++++++----
>  1 file changed, 8 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> index 8427a736f639..b004672d1deb 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> @@ -348,9 +348,13 @@
>  #define PORT_ALPM_LFPS_CTL(tran)
> 	_MMIO_TRANS2(tran, _PORT_ALPM_LFPS_CTL_A)
>  #define  PORT_ALPM_LFPS_CTL_LFPS_START_POLARITY
> 	REG_BIT(31)
>  #define  PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MASK
> 	REG_GENMASK(27, 24)
> -#define  ALPM_CTL_EXTENDED_FAST_WAKE_MIN_LINES		5
> -#define  ALPM_CTL_EXTENDED_FAST_WAKE_TIME(lines)
> 	REG_FIELD_PREP(ALPM_CTL_EXTENDED_FAST_WAKE_TIME_MASK,
> (lines) - ALPM_CTL_EXTENDED_FAST_WAKE_MIN_LINES)
> -#define  ALPM_CTL_AUX_LESS_WAKE_TIME_MASK
> 	REG_GENMASK(5, 0)
> -#define  ALPM_CTL_AUX_LESS_WAKE_TIME(val)
> 	REG_FIELD_PREP(ALPM_CTL_AUX_LESS_WAKE_TIME_MASK, val)
> +#define  PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MIN		7
> +#define  PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(val)
> 	REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MASK,
> (val) - PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MIN)
> +#define  PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION_MASK
> 	REG_GENMASK(20, 16)
> +#define  PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(val)
> 	REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION
> _MASK, val)
> +#define  PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION_MASK
> 	REG_GENMASK(12, 8)
> +#define  PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION(val)
> 	REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION
> _MASK, val)
> +#define  PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK
> 	REG_GENMASK(4, 0)
> +#define  PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION(val)
> 	REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION
> _MASK, val)
> 
>  #endif /* __INTEL_PSR_REGS_H__ */
> --
> 2.34.1