[PATCH 1/5] drm/i915/psr: Calculate PIPE_SRCSZ_ERLY_TPT value

[Kahola, Mika]

> -----Original Message-----
> From: Hogander, Jouni <jouni.hogander at intel.com>
> Sent: Tuesday, March 19, 2024 2:33 PM
> To: intel-gfx at lists.freedesktop.org
> Cc: Kahola, Mika <mika.kahola at intel.com>; Hogander, Jouni <jouni.hogander at intel.com>
> Subject: [PATCH 1/5] drm/i915/psr: Calculate PIPE_SRCSZ_ERLY_TPT value
> 
> When early transport is enabled we need to write PIPE_SRCSZ_ERLY_TPT on every flip doing selective update. This patch
> calculates PIPE_SRCSZ_ERLY_TPT same way as is done for PSR2_MAN_TRK_CTL value and stores i in intel_crtc_state-
> >pipe_srcsz_early_tpt to be written later during flip.
> 
> Bspec: 68927
> 

Reviewed-by: Mika Kahola <mika.kahola at intel.com>

> Signed-off-by: Jouni Högander <jouni.hogander at intel.com>
> ---
>  .../gpu/drm/i915/display/intel_display_types.h   |  2 ++
>  drivers/gpu/drm/i915/display/intel_psr.c         | 16 ++++++++++++++++
>  2 files changed, 18 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 8b9860cefaae..ba573490fd87 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1423,6 +1423,8 @@ struct intel_crtc_state {
> 
>  	u32 psr2_man_track_ctl;
> 
> +	u32 pipe_srcsz_early_tpt;
> +
>  	struct drm_rect psr2_su_area;
> 
>  	/* Variable Refresh Rate state */
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 747761efa4be..cbf9495c7072 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -2075,6 +2075,20 @@ static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,
>  	crtc_state->psr2_man_track_ctl = val;
>  }
> 
> +static u32 psr2_pipe_srcsz_early_tpt_calc(struct intel_crtc_state *crtc_state,
> +					  bool full_update)
> +{
> +	int width, height;
> +
> +	if (!crtc_state->enable_psr2_su_region_et || full_update)
> +		return 0;
> +
> +	width = drm_rect_width(&crtc_state->psr2_su_area);
> +	height = drm_rect_height(&crtc_state->psr2_su_area);
> +
> +	return PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1); }
> +
>  static void clip_area_update(struct drm_rect *overlap_damage_area,
>  			     struct drm_rect *damage_area,
>  			     struct drm_rect *pipe_src)
> @@ -2362,6 +2376,8 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> 
>  skip_sel_fetch_set_loop:
>  	psr2_man_trk_ctl_calc(crtc_state, full_update);
> +	crtc_state->pipe_srcsz_early_tpt =
> +		psr2_pipe_srcsz_early_tpt_calc(crtc_state, full_update);
>  	return 0;
>  }
> 
> --
> 2.34.1