[PATCH 12/19] drm/i915: pass dev_priv explicitly to EDP_PSR2_STATUS
Rodrigo Vivi
rodrigo.vivi at intel.com
Wed May 1 02:21:16 UTC 2024
On Tue, Apr 30, 2024 at 01:10:06PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the EDP_PSR2_STATUS register macro.
>
> Signed-off-by: Jani Nikula <jani.nikula at intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 9 +++++----
> drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +-
> 2 files changed, 6 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 2dca9957a06b..36c08cd3a624 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -2052,7 +2052,7 @@ static void intel_psr_wait_exit_locked(struct intel_dp *intel_dp)
> u32 psr_status_mask;
>
> if (intel_dp->psr.psr2_enabled) {
> - psr_status = EDP_PSR2_STATUS(cpu_transcoder);
> + psr_status = EDP_PSR2_STATUS(dev_priv, cpu_transcoder);
> psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
> } else {
> psr_status = psr_status_reg(dev_priv, cpu_transcoder);
> @@ -2768,7 +2768,7 @@ static int _psr2_ready_for_pipe_update_locked(struct intel_dp *intel_dp)
> * EDP_PSR2_STATUS_STATE_DEEP_SLEEP to be cleared.
> */
> return intel_de_wait_for_clear(dev_priv,
> - EDP_PSR2_STATUS(cpu_transcoder),
> + EDP_PSR2_STATUS(dev_priv, cpu_transcoder),
> EDP_PSR2_STATUS_STATE_DEEP_SLEEP, 50);
> }
>
> @@ -2835,7 +2835,7 @@ static bool __psr_wait_for_idle_locked(struct intel_dp *intel_dp)
> return false;
>
> if (intel_dp->psr.psr2_enabled) {
> - reg = EDP_PSR2_STATUS(cpu_transcoder);
> + reg = EDP_PSR2_STATUS(dev_priv, cpu_transcoder);
> mask = EDP_PSR2_STATUS_STATE_MASK;
> } else {
> reg = psr_status_reg(dev_priv, cpu_transcoder);
> @@ -3467,7 +3467,8 @@ psr_source_status(struct intel_dp *intel_dp, struct seq_file *m)
> "BUF_ON",
> "TG_ON"
> };
> - val = intel_de_read(dev_priv, EDP_PSR2_STATUS(cpu_transcoder));
> + val = intel_de_read(dev_priv,
> + EDP_PSR2_STATUS(dev_priv, cpu_transcoder));
> status_val = REG_FIELD_GET(EDP_PSR2_STATUS_STATE_MASK, val);
> if (status_val < ARRAY_SIZE(live_status))
> status = live_status[status_val];
> diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> index 817bc372bf35..e6c62512512f 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> @@ -215,7 +215,7 @@
>
> #define _PSR2_STATUS_A 0x60940
> #define _PSR2_STATUS_EDP 0x6f940
> -#define EDP_PSR2_STATUS(tran) _MMIO_TRANS2(dev_priv, tran, _PSR2_STATUS_A)
> +#define EDP_PSR2_STATUS(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PSR2_STATUS_A)
> #define EDP_PSR2_STATUS_STATE_MASK REG_GENMASK(31, 28)
> #define EDP_PSR2_STATUS_STATE_DEEP_SLEEP REG_FIELD_PREP(EDP_PSR2_STATUS_STATE_MASK, 0x8)
>
> --
> 2.39.2
>
More information about the Intel-gfx
mailing list