[PATCH 1/5] drm/i915: don't include CML PCI IDs in CFL

[Jani Nikula]

On Tue, 07 May 2024, Rodrigo Vivi <rodrigo.vivi at intel.com> wrote:
> On Tue, May 07, 2024 at 03:56:48PM +0300, Jani Nikula wrote:
>> @@ -535,11 +541,7 @@
>>  	INTEL_WHL_U_GT1_IDS(info), \
>>  	INTEL_WHL_U_GT2_IDS(info), \
>>  	INTEL_WHL_U_GT3_IDS(info), \
>> -	INTEL_AML_CFL_GT2_IDS(info), \
>> -	INTEL_CML_GT1_IDS(info), \
>> -	INTEL_CML_GT2_IDS(info), \
>> -	INTEL_CML_U_GT1_IDS(info), \
>> -	INTEL_CML_U_GT2_IDS(info)
>> +	INTEL_AML_CFL_GT2_IDS(info)
>
> Why only CML and not AML and WHL as well?

Mainly because we don't have a separate enumeration in enum
intel_platform for AML or WHL, while for CML we do. We don't even have
subplatforms for AML or WHL. So we don't need to distinguish them.

That said, we could also have a rule that anything with a name needs to
have a PCI ID macro. Could lean either way.

BR,
Jani.

>
>>  
>>  /* CNL */
>>  #define INTEL_CNL_PORT_F_IDS(info) \
>> -- 
>> 2.39.2
>> 

-- 
Jani Nikula, Intel