✗ Fi.CI.CHECKPATCH: warning for drm/i915/display: remove implicit dev_priv from VRR
Patchwork
patchwork at emeril.freedesktop.org
Wed May 8 16:41:14 UTC 2024
== Series Details ==
Series: drm/i915/display: remove implicit dev_priv from VRR
URL : https://patchwork.freedesktop.org/series/133330/
State : warning
== Summary ==
Error: dim checkpatch failed
b51cea67ab0e drm/i915: pass dev_priv explicitly to TRANS_VRR_CTL
-:70: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#70: FILE: drivers/gpu/drm/i915/i915_reg.h:1236:
+#define TRANS_VRR_CTL(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_CTL_A)
total: 0 errors, 1 warnings, 0 checks, 50 lines checked
467129a9c71a drm/i915: pass dev_priv explicitly to TRANS_VRR_VMAX
de6095cefa23 drm/i915: pass dev_priv explicitly to TRANS_VRR_VMIN
3bd71a922c5b drm/i915: pass dev_priv explicitly to TRANS_VRR_VMAXSHIFT
d88994b3456c drm/i915: pass dev_priv explicitly to TRANS_VRR_STATUS
-:34: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#34: FILE: drivers/gpu/drm/i915/i915_reg.h:1274:
+#define TRANS_VRR_STATUS(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS_A)
total: 0 errors, 1 warnings, 0 checks, 17 lines checked
299de36e3f57 drm/i915: pass dev_priv explicitly to TRANS_VRR_VTOTAL_PREV
e102cc339513 drm/i915: pass dev_priv explicitly to TRANS_VRR_FLIPLINE
-:31: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#31: FILE: drivers/gpu/drm/i915/display/intel_vrr.c:316:
+ TRANS_VRR_FLIPLINE(dev_priv, cpu_transcoder)) + 1;
total: 0 errors, 1 warnings, 0 checks, 26 lines checked
1f9d98de293e drm/i915: pass dev_priv explicitly to TRANS_VRR_STATUS2
48ea1d97c2f0 drm/i915: pass dev_priv explicitly to TRANS_PUSH
05c90497a890 drm/i915: pass dev_priv explicitly to TRANS_VRR_VSYNC
-:31: ERROR:CODE_INDENT: code indent should use tabs where possible
#31: FILE: drivers/gpu/drm/i915/display/intel_vrr.c:295:
+^I^I TRANS_VRR_VSYNC(dev_priv, cpu_transcoder), 0);$
-:54: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#54: FILE: drivers/gpu/drm/i915/i915_reg.h:1325:
+#define TRANS_VRR_VSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VSYNC_A)
total: 1 errors, 1 warnings, 0 checks, 35 lines checked
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