[PATCH 06/16] drm/i915/gvt: Use the proper PLANE_AUX_OFFSET() define

[Jani Nikula]

On Fri, 10 May 2024, Ville Syrjala <ville.syrjala at linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
>
> Stop hand rolling PLANE_AUX_OFFSET() and just use the real thing.
>
> Cc: Zhenyu Wang <zhenyuw at linux.intel.com>
> CC: Zhi Wang <zhi.wang.linux at gmail.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula at intel.com>

> ---
>  drivers/gpu/drm/i915/gvt/handlers.c         | 24 ++++++++++-----------
>  drivers/gpu/drm/i915/gvt/reg.h              |  2 --
>  drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 24 ++++++++++-----------
>  3 files changed, 24 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index 6b02612ddef5..6f633035618e 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -2693,20 +2693,20 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
>  	MMIO_DH(PLANE_AUX_DIST(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
>  	MMIO_DH(PLANE_AUX_DIST(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
>  
> -	MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL);
> -	MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL);
> -	MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL);
> -	MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL);
> +	MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
> +	MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
> +	MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
> +	MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
>  
> -	MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL);
> -	MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL);
> -	MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL);
> -	MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL);
> +	MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
> +	MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
> +	MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
> +	MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
>  
> -	MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL);
> -	MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL);
> -	MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
> -	MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
> +	MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
> +	MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
> +	MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
> +	MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
>  
>  	MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
>  
> diff --git a/drivers/gpu/drm/i915/gvt/reg.h b/drivers/gpu/drm/i915/gvt/reg.h
> index e8a56faafe95..90d8eb1761a3 100644
> --- a/drivers/gpu/drm/i915/gvt/reg.h
> +++ b/drivers/gpu/drm/i915/gvt/reg.h
> @@ -57,8 +57,6 @@
>  
>  #define VGT_SPRSTRIDE(pipe)	_PIPE(pipe, _SPRA_STRIDE, _PLANE_STRIDE_2_B)
>  
> -#define _REG_701C4(pipe, plane) (0x701c4 + pipe * 0x1000 + (plane - 1) * 0x100)
> -
>  #define SKL_FLIP_EVENT(pipe, plane) (PRIMARY_A_FLIP_DONE + (plane) * 3 + (pipe))
>  
>  #define REG50080_FLIP_TYPE_MASK	0x3
> diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> index cf45342a6db0..ad3bf60855bc 100644
> --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> @@ -1018,18 +1018,18 @@ static int iterate_skl_plus_mmio(struct intel_gvt_mmio_table_iter *iter)
>  	MMIO_D(PLANE_AUX_DIST(PIPE_C, 1));
>  	MMIO_D(PLANE_AUX_DIST(PIPE_C, 2));
>  	MMIO_D(PLANE_AUX_DIST(PIPE_C, 3));
> -	MMIO_D(_MMIO(_REG_701C4(PIPE_A, 1)));
> -	MMIO_D(_MMIO(_REG_701C4(PIPE_A, 2)));
> -	MMIO_D(_MMIO(_REG_701C4(PIPE_A, 3)));
> -	MMIO_D(_MMIO(_REG_701C4(PIPE_A, 4)));
> -	MMIO_D(_MMIO(_REG_701C4(PIPE_B, 1)));
> -	MMIO_D(_MMIO(_REG_701C4(PIPE_B, 2)));
> -	MMIO_D(_MMIO(_REG_701C4(PIPE_B, 3)));
> -	MMIO_D(_MMIO(_REG_701C4(PIPE_B, 4)));
> -	MMIO_D(_MMIO(_REG_701C4(PIPE_C, 1)));
> -	MMIO_D(_MMIO(_REG_701C4(PIPE_C, 2)));
> -	MMIO_D(_MMIO(_REG_701C4(PIPE_C, 3)));
> -	MMIO_D(_MMIO(_REG_701C4(PIPE_C, 4)));
> +	MMIO_D(PLANE_AUX_OFFSET(PIPE_A, 0));
> +	MMIO_D(PLANE_AUX_OFFSET(PIPE_A, 1));
> +	MMIO_D(PLANE_AUX_OFFSET(PIPE_A, 2));
> +	MMIO_D(PLANE_AUX_OFFSET(PIPE_A, 3));
> +	MMIO_D(PLANE_AUX_OFFSET(PIPE_B, 0));
> +	MMIO_D(PLANE_AUX_OFFSET(PIPE_B, 1));
> +	MMIO_D(PLANE_AUX_OFFSET(PIPE_B, 2));
> +	MMIO_D(PLANE_AUX_OFFSET(PIPE_B, 3));
> +	MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 0));
> +	MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 1));
> +	MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 2));
> +	MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 3));
>  	MMIO_D(_MMIO(_PLANE_CTL_3_A));
>  	MMIO_D(_MMIO(_PLANE_CTL_3_B));
>  	MMIO_D(_MMIO(0x72380));

-- 
Jani Nikula, Intel