[PATCH v2 0/2] drm/i915/display: Add comparison for pipe config for MTL+ >

[Mika Kahola]

Currently, we may bump into pll mismatch errors during the
state verification stage. This happens when we try to use
fastset instead of full modeset. Hence, we would need to add
a check for pipe configuration to ensure that the sw and the
hw configuration will match. In case of hw and sw mismatch,
we would need to disable fastset and use full modeset instead.

However, first we need to revert the patch that disables fastset
for C10.

v2: Fix C10 error on PLL comparison (BAT)
    Use memcmp instead of fixed loops for pll config
    comparison (Jani)
    Clean up and use intel_cx0pll_dump_hw_state() to dump
    pll information (Jani)

Signed-off-by: Mika Kahola <mika.kahola at intel.com>

Mika Kahola (2):
  drm/i915/display: Revert "drm/i915/display: Skip C10 state
    verification in case of fastset"
  drm/i915/display: Add compare config for MTL+ platforms

 drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 80 ++++++++++++++++---
 drivers/gpu/drm/i915/display/intel_cx0_phy.h  |  8 +-
 drivers/gpu/drm/i915/display/intel_display.c  | 33 ++++++++
 drivers/gpu/drm/i915/display/intel_dpll_mgr.h |  1 +
 4 files changed, 109 insertions(+), 13 deletions(-)

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2.34.1